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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
13 The i.MX SoC family has multiple buses for which clock frequency (and
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/fsl/
Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx8m-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Family Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
19 - fsl,imx8mm-ccm
20 - fsl,imx8mn-ccm
21 - fsl,imx8mp-ccm
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/kernel/linux/linux-5.10/drivers/devfreq/
Dimx-bus.c1 // SPDX-License-Identifier: GPL-2.0
43 *freq = clk_get_rate(priv->clk); in imx_bus_get_cur_freq()
53 stat->busy_time = 0; in imx_bus_get_dev_status()
54 stat->total_time = 0; in imx_bus_get_dev_status()
55 stat->current_frequency = clk_get_rate(priv->clk); in imx_bus_get_dev_status()
65 platform_device_unregister(priv->icc_pdev); in imx_bus_exit()
68 /* imx_bus_init_icc() - register matching icc provider if required */
74 if (!of_get_property(dev->of_node, "#interconnect-cells", 0)) in imx_bus_init_icc()
87 priv->icc_pdev = platform_device_register_data( in imx_bus_init_icc()
88 dev, icc_driver_name, -1, NULL, 0); in imx_bus_init_icc()
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Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
50 * +----------+ | | |
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,irqsteer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
15 - const: fsl,imx-irqsteer
16 - items:
17 - const: fsl,imx8m-irqsteer
18 - const: fsl,imx-irqsteer
29 - description: output interrupt 0
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pico-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "TechNexion PICO-PI-8M";
16 compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
19 stdout-path = &uart1;
22 pmic_osc: clock-pmic {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <32768>;
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Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
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Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-frac-pll.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the fractional plls found in the imx8m SOCs
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
48 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, in clk_wait_lock()
57 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) in clk_wait_ack()
61 return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, in clk_wait_ack()
70 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_prepare()
72 writel_relaxed(val, pll->base + PLL_CFG0); in clk_pll_prepare()
82 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_unprepare()
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/kernel/linux/linux-5.10/drivers/perf/
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
95 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
117 int cap = (long)ea->var; in ddr_perf_filter_cap_show()
147 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
169 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
181 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
182 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0001_linux_arch.patch7 Change-Id: I8c7b42f8858212fb4b2d56a871d3f4d5afc73954
9 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
11 --- a/arch/arm64/Kconfig
13 @@ -183,7 +183,6 @@ config ARM64
17 - select HOLES_IN_ZONE
21 @@ -1023,6 +1022,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
31 @@ -1148,7 +1150,7 @@ config XEN
35 - int
40 @@ -1182,15 +1184,6 @@ config UNMAP_KERNEL_AT_EL0
44 -config MITIGATE_SPECTRE_BRANCH_HISTORY
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0033_linux_drivers_soc_scsi_spi_tee_thermal.patch7 Change-Id: I1ba947d26a24ae6708961a663867e136c1171c8d
9 diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c
11 --- a/drivers/scsi/scsi_error.c
13 @@ -63,6 +63,13 @@ static int scsi_eh_try_stu(struct scsi_cmnd *scmd);
23 +/* called with shost->host_lock held */
26 lockdep_assert_held(shost->host_lock);
27 @@ -72,6 +79,11 @@ void scsi_eh_wakeup(struct Scsi_Host *shost)
28 wake_up_process(shost->ehandler);
31 + } else if ((shost->host_failed > 0) || (sg_io_buffer_hack != NULL)) {
33 + wake_up_process(shost->ehandler);
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D0031_linux_drivers_perf_phy_pinctrl_ptp_pwm.patch7 Change-Id: I50a0069a60f92f57dd6112f6a9700811be19e564
9 diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
11 --- a/drivers/perf/fsl_imx8_ddr_perf.c
13 @@ -5,6 +5,7 @@
21 @@ -14,12 +15,15 @@
37 @@ -28,9 +32,18 @@
56 @@ -40,32 +53,56 @@
80 -static const struct fsl_ddr_devtype_data imx8_devtype_data;
106 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
107 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
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D0034_linux_drivers_usb_vfio_wdt_tty_uio.patch7 Change-Id: I1b7e905c318654a235ffe85d3c392289593c1c9d
9 diff --git a/drivers/Kconfig b/drivers/Kconfig
11 --- a/drivers/Kconfig
13 @@ -238,6 +238,8 @@ source "drivers/counter/Kconfig"
22 diff --git a/drivers/Makefile b/drivers/Makefile
24 --- a/drivers/Makefile
26 @@ -192,5 +192,6 @@ obj-$(CONFIG_GNSS) += gnss/
27 obj-$(CONFIG_INTERCONNECT) += interconnect/
28 obj-$(CONFIG_COUNTER) += counter/
29 obj-$(CONFIG_MOST) += most/
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D0038_linux_drivers_mxc.patch7 Change-Id: I2f6375e746087a874cbea0a4240e92abfded3358
9 diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig
12 --- /dev/null
14 @@ -0,0 +1,38 @@
34 +source "drivers/mxc/gpu-viv/Kconfig"
53 diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile
56 --- /dev/null
58 @@ -0,0 +1,10 @@
59 +obj-$(CONFIG_MXC_GPU_VIV) += gpu-viv/
60 +obj-$(CONFIG_MXC_SIM) += sim/
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/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch1 diff --git a/drivers/Makefile b/drivers/Makefile
3 --- a/drivers/Makefile
5 @@ -6,6 +6,8 @@
6 # Rewritten to use lists instead of if-statements.
11 obj-y += irqchip/
12 obj-y += bus/
14 diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
16 --- a/drivers/block/nbd.c
18 @@ -2398,12 +2398,6 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info)
22 - if (!dev_list) {
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