1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ac_binary.h"
25
26 #include "ac_gpu_info.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29
30 #ifndef _WIN32
31 #include <gelf.h>
32 #include <libelf.h>
33 #endif
34 #include <sid.h>
35 #include <stdio.h>
36
37 #define SPILLED_SGPRS 0x4
38 #define SPILLED_VGPRS 0x8
39
40 /* Parse configuration data in .AMDGPU.config section format. */
ac_parse_shader_binary_config(const char * data,size_t nbytes,unsigned wave_size,const struct radeon_info * info,struct ac_shader_config * conf)41 void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wave_size,
42 const struct radeon_info *info, struct ac_shader_config *conf)
43 {
44 for (size_t i = 0; i < nbytes; i += 8) {
45 unsigned reg = util_le32_to_cpu(*(uint32_t *)(data + i));
46 unsigned value = util_le32_to_cpu(*(uint32_t *)(data + i + 4));
47 switch (reg) {
48 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
49 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
50 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
51 case R_00B848_COMPUTE_PGM_RSRC1:
52 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
53 if (wave_size == 32 || info->wave64_vgpr_alloc_granularity == 8)
54 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
55 else
56 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
57
58 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
59 /* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
60 conf->float_mode = G_00B028_FLOAT_MODE(value);
61 conf->rsrc1 = value;
62 break;
63 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
64 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
65 /* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
66 conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
67 conf->rsrc2 = value;
68 break;
69 case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
70 conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
71 conf->rsrc2 = value;
72 break;
73 case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
74 conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
75 conf->rsrc2 = value;
76 break;
77 case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
78 conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
79 conf->rsrc2 = value;
80 break;
81 case R_00B84C_COMPUTE_PGM_RSRC2:
82 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
83 conf->rsrc2 = value;
84 break;
85 case R_00B8A0_COMPUTE_PGM_RSRC3:
86 conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
87 conf->rsrc3 = value;
88 break;
89 case R_0286CC_SPI_PS_INPUT_ENA:
90 conf->spi_ps_input_ena = value;
91 break;
92 case R_0286D0_SPI_PS_INPUT_ADDR:
93 conf->spi_ps_input_addr = value;
94 break;
95 case R_0286E8_SPI_TMPRING_SIZE:
96 case R_00B860_COMPUTE_TMPRING_SIZE:
97 if (info->gfx_level >= GFX11)
98 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 256;
99 else
100 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 1024;
101 break;
102 case SPILLED_SGPRS:
103 conf->spilled_sgprs = value;
104 break;
105 case SPILLED_VGPRS:
106 conf->spilled_vgprs = value;
107 break;
108 default: {
109 static bool printed;
110
111 if (!printed) {
112 fprintf(stderr,
113 "Warning: LLVM emitted unknown "
114 "config register: 0x%x\n",
115 reg);
116 printed = true;
117 }
118 } break;
119 }
120 }
121
122 if (!conf->spi_ps_input_addr)
123 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
124
125 /* GFX 10.3 internally:
126 * - aligns VGPRS to 16 for Wave32 and 8 for Wave64
127 * - aligns LDS to 1024
128 *
129 * For shader-db stats, set num_vgprs that the hw actually uses.
130 */
131 if (info->gfx_level == GFX10_3) {
132 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
133 }
134
135 /* Enable 64-bit and 16-bit denormals, because there is no performance
136 * cost.
137 *
138 * Don't enable denormals for 32-bit floats, because:
139 * - denormals disable output modifiers
140 * - denormals break v_mad_f32
141 * - GFX6 & GFX7 would be very slow
142 */
143 conf->float_mode &= ~V_00B028_FP_32_DENORMS;
144 conf->float_mode |= V_00B028_FP_16_64_DENORMS;
145 }
146