1 /*
2 * Copyright © 2021 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "ac_nir.h"
26 #include "nir.h"
27 #include "nir_builder.h"
28
29 static nir_ssa_def *
try_extract_additions(nir_builder * b,nir_ssa_scalar scalar,uint64_t * out_const,nir_ssa_def ** out_offset)30 try_extract_additions(nir_builder *b, nir_ssa_scalar scalar, uint64_t *out_const,
31 nir_ssa_def **out_offset)
32 {
33 if (!nir_ssa_scalar_is_alu(scalar) || nir_ssa_scalar_alu_op(scalar) != nir_op_iadd)
34 return NULL;
35
36 nir_alu_instr *alu = nir_instr_as_alu(scalar.def->parent_instr);
37 nir_ssa_scalar src0 = nir_ssa_scalar_chase_alu_src(scalar, 0);
38 nir_ssa_scalar src1 = nir_ssa_scalar_chase_alu_src(scalar, 1);
39
40 for (unsigned i = 0; i < 2; ++i) {
41 nir_ssa_scalar src = i ? src1 : src0;
42 if (nir_ssa_scalar_is_const(src)) {
43 *out_const += nir_ssa_scalar_as_uint(src);
44 } else if (nir_ssa_scalar_is_alu(src) && nir_ssa_scalar_alu_op(src) == nir_op_u2u64) {
45 nir_ssa_scalar offset_scalar = nir_ssa_scalar_chase_alu_src(src, 0);
46 nir_ssa_def *offset = nir_channel(b, offset_scalar.def, offset_scalar.comp);
47 if (*out_offset)
48 *out_offset = nir_iadd(b, *out_offset, offset);
49 else
50 *out_offset = offset;
51 } else {
52 continue;
53 }
54
55 nir_ssa_def *replace_src =
56 try_extract_additions(b, i == 1 ? src0 : src1, out_const, out_offset);
57 return replace_src ? replace_src : nir_ssa_for_alu_src(b, alu, 1 - i);
58 }
59
60 nir_ssa_def *replace_src0 = try_extract_additions(b, src0, out_const, out_offset);
61 nir_ssa_def *replace_src1 = try_extract_additions(b, src1, out_const, out_offset);
62 if (!replace_src0 && !replace_src1)
63 return NULL;
64
65 replace_src0 = replace_src0 ? replace_src0 : nir_channel(b, src0.def, src0.comp);
66 replace_src1 = replace_src1 ? replace_src1 : nir_channel(b, src1.def, src1.comp);
67 return nir_iadd(b, replace_src0, replace_src1);
68 }
69
70 static bool
process_instr(nir_builder * b,nir_instr * instr,void * _)71 process_instr(nir_builder *b, nir_instr *instr, void *_)
72 {
73 if (instr->type != nir_instr_type_intrinsic)
74 return false;
75
76 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
77
78 nir_intrinsic_op op;
79 switch (intrin->intrinsic) {
80 case nir_intrinsic_load_global:
81 case nir_intrinsic_load_global_constant:
82 op = nir_intrinsic_load_global_amd;
83 break;
84 case nir_intrinsic_global_atomic_add:
85 op = nir_intrinsic_global_atomic_add_amd;
86 break;
87 case nir_intrinsic_global_atomic_imin:
88 op = nir_intrinsic_global_atomic_imin_amd;
89 break;
90 case nir_intrinsic_global_atomic_umin:
91 op = nir_intrinsic_global_atomic_umin_amd;
92 break;
93 case nir_intrinsic_global_atomic_imax:
94 op = nir_intrinsic_global_atomic_imax_amd;
95 break;
96 case nir_intrinsic_global_atomic_umax:
97 op = nir_intrinsic_global_atomic_umax_amd;
98 break;
99 case nir_intrinsic_global_atomic_and:
100 op = nir_intrinsic_global_atomic_and_amd;
101 break;
102 case nir_intrinsic_global_atomic_or:
103 op = nir_intrinsic_global_atomic_or_amd;
104 break;
105 case nir_intrinsic_global_atomic_xor:
106 op = nir_intrinsic_global_atomic_xor_amd;
107 break;
108 case nir_intrinsic_global_atomic_exchange:
109 op = nir_intrinsic_global_atomic_exchange_amd;
110 break;
111 case nir_intrinsic_global_atomic_fadd:
112 op = nir_intrinsic_global_atomic_fadd_amd;
113 break;
114 case nir_intrinsic_global_atomic_fmin:
115 op = nir_intrinsic_global_atomic_fmin_amd;
116 break;
117 case nir_intrinsic_global_atomic_fmax:
118 op = nir_intrinsic_global_atomic_fmax_amd;
119 break;
120 case nir_intrinsic_global_atomic_comp_swap:
121 op = nir_intrinsic_global_atomic_comp_swap_amd;
122 break;
123 case nir_intrinsic_global_atomic_fcomp_swap:
124 op = nir_intrinsic_global_atomic_fcomp_swap_amd;
125 break;
126 case nir_intrinsic_store_global:
127 op = nir_intrinsic_store_global_amd;
128 break;
129 default:
130 return false;
131 }
132 unsigned addr_src_idx = op == nir_intrinsic_store_global_amd ? 1 : 0;
133
134 nir_src *addr_src = &intrin->src[addr_src_idx];
135
136 uint64_t off_const = 0;
137 nir_ssa_def *offset = NULL;
138 nir_ssa_scalar src = {addr_src->ssa, 0};
139 b->cursor = nir_after_instr(addr_src->ssa->parent_instr);
140 nir_ssa_def *addr = try_extract_additions(b, src, &off_const, &offset);
141 addr = addr ? addr : addr_src->ssa;
142
143 b->cursor = nir_before_instr(&intrin->instr);
144
145 if (off_const > UINT32_MAX) {
146 addr = nir_iadd_imm(b, addr, off_const);
147 off_const = 0;
148 }
149
150 nir_intrinsic_instr *new_intrin = nir_intrinsic_instr_create(b->shader, op);
151
152 new_intrin->num_components = intrin->num_components;
153
154 if (op != nir_intrinsic_store_global_amd)
155 nir_ssa_dest_init(&new_intrin->instr, &new_intrin->dest, intrin->dest.ssa.num_components,
156 intrin->dest.ssa.bit_size, NULL);
157
158 unsigned num_src = nir_intrinsic_infos[intrin->intrinsic].num_srcs;
159 for (unsigned i = 0; i < num_src; i++)
160 new_intrin->src[i] = nir_src_for_ssa(intrin->src[i].ssa);
161 new_intrin->src[num_src] = nir_src_for_ssa(offset ? offset : nir_imm_zero(b, 1, 32));
162 new_intrin->src[addr_src_idx] = nir_src_for_ssa(addr);
163
164 if (nir_intrinsic_has_access(intrin))
165 nir_intrinsic_set_access(new_intrin, nir_intrinsic_access(intrin));
166 if (nir_intrinsic_has_align_mul(intrin))
167 nir_intrinsic_set_align_mul(new_intrin, nir_intrinsic_align_mul(intrin));
168 if (nir_intrinsic_has_align_offset(intrin))
169 nir_intrinsic_set_align_offset(new_intrin, nir_intrinsic_align_offset(intrin));
170 if (nir_intrinsic_has_write_mask(intrin))
171 nir_intrinsic_set_write_mask(new_intrin, nir_intrinsic_write_mask(intrin));
172 nir_intrinsic_set_base(new_intrin, off_const);
173
174 nir_builder_instr_insert(b, &new_intrin->instr);
175 if (op != nir_intrinsic_store_global_amd)
176 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, &new_intrin->dest.ssa);
177 nir_instr_remove(&intrin->instr);
178
179 return true;
180 }
181
182 bool
ac_nir_lower_global_access(nir_shader * shader)183 ac_nir_lower_global_access(nir_shader *shader)
184 {
185 return nir_shader_instructions_pass(shader, process_instr,
186 nir_metadata_block_index | nir_metadata_dominance, NULL);
187 }
188