1/****************************************************************************** 2 * @file gcc_arm.ld 3 * @brief GNU Linker Script for Cortex-M based device 4 * @version V2.2.0 5 * @date 16. December 2020 6 ******************************************************************************/ 7/* 8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25/* 26 *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 27 */ 28 29/*---------------------- Flash Configuration ---------------------------------- 30 <h> Flash Configuration 31 <o0> Flash Base Address <0x0-0xFFFFFFFF:8> 32 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 </h> 34 -----------------------------------------------------------------------------*/ 35__ROM_BASE = 0x00000000; 36__ROM_SIZE = 0x00040000; 37 38/*--------------------- Embedded RAM Configuration ---------------------------- 39 <h> RAM Configuration 40 <o0> RAM Base Address <0x0-0xFFFFFFFF:8> 41 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 42 </h> 43 -----------------------------------------------------------------------------*/ 44__RAM_BASE = 0x20000000; 45__RAM_SIZE = 0x00020000; 46 47/*--------------------- Stack / Heap Configuration ---------------------------- 48 <h> Stack / Heap Configuration 49 <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 50 <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 51 </h> 52 -----------------------------------------------------------------------------*/ 53__STACK_SIZE = 0x00000400; 54__HEAP_SIZE = 0x00000C00; 55 56/* 57 *-------------------- <<< end of configuration section >>> ------------------- 58 */ 59 60/* ARMv8-M stack sealing: 61 to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 62 */ 63__STACKSEAL_SIZE = 0; 64 65 66MEMORY 67{ 68 FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE 69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE 70} 71 72/* Linker script to place sections and symbol values. Should be used together 73 * with other linker script that defines memory regions FLASH and RAM. 74 * It references following symbols, which must be defined in code: 75 * Reset_Handler : Entry of reset handler 76 * 77 * It defines following symbols, which code can use without definition: 78 * __exidx_start 79 * __exidx_end 80 * __copy_table_start__ 81 * __copy_table_end__ 82 * __zero_table_start__ 83 * __zero_table_end__ 84 * __etext 85 * __data_start__ 86 * __preinit_array_start 87 * __preinit_array_end 88 * __init_array_start 89 * __init_array_end 90 * __fini_array_start 91 * __fini_array_end 92 * __data_end__ 93 * __bss_start__ 94 * __bss_end__ 95 * __end__ 96 * end 97 * __HeapLimit 98 * __StackLimit 99 * __StackTop 100 * __stack 101 * __StackSeal (only if ARMv8-M stack sealing is used) 102 */ 103ENTRY(Reset_Handler) 104 105SECTIONS 106{ 107 .text : 108 { 109 KEEP(*(.vectors)) 110 *(.text*) 111 112 KEEP(*(.init)) 113 KEEP(*(.fini)) 114 115 /* .ctors */ 116 *crtbegin.o(.ctors) 117 *crtbegin?.o(.ctors) 118 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 119 *(SORT(.ctors.*)) 120 *(.ctors) 121 122 /* .dtors */ 123 *crtbegin.o(.dtors) 124 *crtbegin?.o(.dtors) 125 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 126 *(SORT(.dtors.*)) 127 *(.dtors) 128 129 *(.rodata*) 130 131 KEEP(*(.eh_frame*)) 132 } > FLASH 133 134 /* 135 * SG veneers: 136 * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address 137 * must be set, either with the command line option �--section-start� or in a linker script, 138 * to indicate where to place these veneers in memory. 139 */ 140/* 141 .gnu.sgstubs : 142 { 143 . = ALIGN(32); 144 } > FLASH 145*/ 146 .ARM.extab : 147 { 148 *(.ARM.extab* .gnu.linkonce.armextab.*) 149 } > FLASH 150 151 __exidx_start = .; 152 .ARM.exidx : 153 { 154 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 155 } > FLASH 156 __exidx_end = .; 157 158 .copy.table : 159 { 160 . = ALIGN(4); 161 __copy_table_start__ = .; 162 163 LONG (__etext) 164 LONG (__data_start__) 165 LONG ((__data_end__ - __data_start__) / 4) 166 167 /* Add each additional data section here */ 168/* 169 LONG (__etext2) 170 LONG (__data2_start__) 171 LONG ((__data2_end__ - __data2_start__) / 4) 172*/ 173 __copy_table_end__ = .; 174 } > FLASH 175 176 .zero.table : 177 { 178 . = ALIGN(4); 179 __zero_table_start__ = .; 180 /* Add each additional bss section here */ 181/* 182 LONG (__bss2_start__) 183 LONG ((__bss2_end__ - __bss2_start__) / 4) 184*/ 185 __zero_table_end__ = .; 186 } > FLASH 187 188 /** 189 * Location counter can end up 2byte aligned with narrow Thumb code but 190 * __etext is assumed by startup code to be the LMA of a section in RAM 191 * which must be 4byte aligned 192 */ 193 __etext = ALIGN (4); 194 195 .data : AT (__etext) 196 { 197 __data_start__ = .; 198 *(vtable) 199 *(.data) 200 *(.data.*) 201 202 . = ALIGN(4); 203 /* preinit data */ 204 PROVIDE_HIDDEN (__preinit_array_start = .); 205 KEEP(*(.preinit_array)) 206 PROVIDE_HIDDEN (__preinit_array_end = .); 207 208 . = ALIGN(4); 209 /* init data */ 210 PROVIDE_HIDDEN (__init_array_start = .); 211 KEEP(*(SORT(.init_array.*))) 212 KEEP(*(.init_array)) 213 PROVIDE_HIDDEN (__init_array_end = .); 214 215 . = ALIGN(4); 216 /* finit data */ 217 PROVIDE_HIDDEN (__fini_array_start = .); 218 KEEP(*(SORT(.fini_array.*))) 219 KEEP(*(.fini_array)) 220 PROVIDE_HIDDEN (__fini_array_end = .); 221 222 KEEP(*(.jcr*)) 223 . = ALIGN(4); 224 /* All data end */ 225 __data_end__ = .; 226 227 } > RAM 228 229 /* 230 * Secondary data section, optional 231 * 232 * Remember to add each additional data section 233 * to the .copy.table above to asure proper 234 * initialization during startup. 235 */ 236/* 237 __etext2 = ALIGN (4); 238 239 .data2 : AT (__etext2) 240 { 241 . = ALIGN(4); 242 __data2_start__ = .; 243 *(.data2) 244 *(.data2.*) 245 . = ALIGN(4); 246 __data2_end__ = .; 247 248 } > RAM2 249*/ 250 251 .bss : 252 { 253 . = ALIGN(4); 254 __bss_start__ = .; 255 *(.bss) 256 *(.bss.*) 257 *(COMMON) 258 . = ALIGN(4); 259 __bss_end__ = .; 260 } > RAM AT > RAM 261 262 /* 263 * Secondary bss section, optional 264 * 265 * Remember to add each additional bss section 266 * to the .zero.table above to asure proper 267 * initialization during startup. 268 */ 269/* 270 .bss2 : 271 { 272 . = ALIGN(4); 273 __bss2_start__ = .; 274 *(.bss2) 275 *(.bss2.*) 276 . = ALIGN(4); 277 __bss2_end__ = .; 278 } > RAM2 AT > RAM2 279*/ 280 281 .heap (COPY) : 282 { 283 . = ALIGN(8); 284 __end__ = .; 285 PROVIDE(end = .); 286 . = . + __HEAP_SIZE; 287 . = ALIGN(8); 288 __HeapLimit = .; 289 } > RAM 290 291 .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : 292 { 293 . = ALIGN(8); 294 __StackLimit = .; 295 . = . + __STACK_SIZE; 296 . = ALIGN(8); 297 __StackTop = .; 298 } > RAM 299 PROVIDE(__stack = __StackTop); 300 301 /* ARMv8-M stack sealing: 302 to use ARMv8-M stack sealing uncomment '.stackseal' section 303 */ 304/* 305 .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : 306 { 307 . = ALIGN(8); 308 __StackSeal = .; 309 . = . + 8; 310 . = ALIGN(8); 311 } > RAM 312*/ 313 314 /* Check if data + heap + stack exceeds RAM limit */ 315 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 316} 317