1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "compiler/nir/nir.h"
26 #include "radeon_uvd_enc.h"
27 #include "radeon_vce.h"
28 #include "radeon_video.h"
29 #include "si_pipe.h"
30 #include "util/u_cpu_detect.h"
31 #include "util/u_screen.h"
32 #include "util/u_video.h"
33 #include "vl/vl_decoder.h"
34 #include "vl/vl_video_buffer.h"
35 #include <sys/utsname.h>
36
si_get_vendor(struct pipe_screen * pscreen)37 static const char *si_get_vendor(struct pipe_screen *pscreen)
38 {
39 return "AMD";
40 }
41
si_get_device_vendor(struct pipe_screen * pscreen)42 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
43 {
44 return "AMD";
45 }
46
si_get_param(struct pipe_screen * pscreen,enum pipe_cap param)47 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
48 {
49 struct si_screen *sscreen = (struct si_screen *)pscreen;
50
51 /* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */
52 bool enable_sparse = sscreen->info.gfx_level >= GFX9 &&
53 sscreen->info.has_sparse_vm_mappings;
54
55 switch (param) {
56 /* Supported features (boolean caps). */
57 case PIPE_CAP_ACCELERATED:
58 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
59 case PIPE_CAP_ANISOTROPIC_FILTER:
60 case PIPE_CAP_POINT_SPRITE:
61 case PIPE_CAP_OCCLUSION_QUERY:
62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
63 case PIPE_CAP_TEXTURE_SHADOW_LOD:
64 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
65 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
66 case PIPE_CAP_TEXTURE_SWIZZLE:
67 case PIPE_CAP_DEPTH_CLIP_DISABLE:
68 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
69 case PIPE_CAP_SHADER_STENCIL_EXPORT:
70 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
71 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
72 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
73 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
74 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
75 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
76 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
77 case PIPE_CAP_PRIMITIVE_RESTART:
78 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
79 case PIPE_CAP_CONDITIONAL_RENDER:
80 case PIPE_CAP_TEXTURE_BARRIER:
81 case PIPE_CAP_INDEP_BLEND_ENABLE:
82 case PIPE_CAP_INDEP_BLEND_FUNC:
83 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
84 case PIPE_CAP_START_INSTANCE:
85 case PIPE_CAP_NPOT_TEXTURES:
86 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
87 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
88 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
89 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
90 case PIPE_CAP_VS_INSTANCEID:
91 case PIPE_CAP_COMPUTE:
92 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
93 case PIPE_CAP_VS_LAYER_VIEWPORT:
94 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
96 case PIPE_CAP_SAMPLE_SHADING:
97 case PIPE_CAP_DRAW_INDIRECT:
98 case PIPE_CAP_CLIP_HALFZ:
99 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
100 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
101 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
102 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
103 case PIPE_CAP_TGSI_TEXCOORD:
104 case PIPE_CAP_FS_FINE_DERIVATIVE:
105 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
106 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
107 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
108 case PIPE_CAP_DEPTH_BOUNDS_TEST:
109 case PIPE_CAP_SAMPLER_VIEW_TARGET:
110 case PIPE_CAP_TEXTURE_QUERY_LOD:
111 case PIPE_CAP_TEXTURE_GATHER_SM5:
112 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
113 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
114 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
115 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
116 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
117 case PIPE_CAP_INVALIDATE_BUFFER:
118 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
119 case PIPE_CAP_QUERY_BUFFER_OBJECT:
120 case PIPE_CAP_QUERY_MEMORY_INFO:
121 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
122 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
123 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
124 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
125 case PIPE_CAP_STRING_MARKER:
126 case PIPE_CAP_CLEAR_TEXTURE:
127 case PIPE_CAP_CULL_DISTANCE:
128 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
129 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
130 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
131 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
132 case PIPE_CAP_DOUBLES:
133 case PIPE_CAP_TGSI_TEX_TXF_LZ:
134 case PIPE_CAP_TES_LAYER_VIEWPORT:
135 case PIPE_CAP_BINDLESS_TEXTURE:
136 case PIPE_CAP_QUERY_TIMESTAMP:
137 case PIPE_CAP_QUERY_TIME_ELAPSED:
138 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
139 case PIPE_CAP_MEMOBJ:
140 case PIPE_CAP_LOAD_CONSTBUF:
141 case PIPE_CAP_INT64:
142 case PIPE_CAP_INT64_DIVMOD:
143 case PIPE_CAP_SHADER_CLOCK:
144 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
145 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
146 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
147 case PIPE_CAP_SHADER_BALLOT:
148 case PIPE_CAP_SHADER_GROUP_VOTE:
149 case PIPE_CAP_FBFETCH:
150 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
151 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
152 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
153 case PIPE_CAP_TGSI_DIV:
154 case PIPE_CAP_PACKED_UNIFORMS:
155 case PIPE_CAP_GL_SPIRV:
156 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
157 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
158 case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
159 case PIPE_CAP_SHADER_ATOMIC_INT64:
160 case PIPE_CAP_FRONTEND_NOOP:
161 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
162 case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
163 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
164 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
165 case PIPE_CAP_IMAGE_STORE_FORMATTED:
166 case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
167 case PIPE_CAP_QUERY_SO_OVERFLOW:
168 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
169 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
170 case PIPE_CAP_TEXTURE_MULTISAMPLE:
171 return 1;
172
173 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
174 return PIPE_TEXTURE_TRANSFER_BLIT;
175
176 case PIPE_CAP_DRAW_VERTEX_STATE:
177 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
178
179 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
180 return sscreen->info.gfx_level < GFX11;
181
182 case PIPE_CAP_GLSL_ZERO_INIT:
183 return 2;
184
185 case PIPE_CAP_GENERATE_MIPMAP:
186 case PIPE_CAP_SEAMLESS_CUBE_MAP:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
188 case PIPE_CAP_CUBE_MAP_ARRAY:
189 return sscreen->info.has_3d_cube_border_color_mipmap;
190
191 case PIPE_CAP_POST_DEPTH_COVERAGE:
192 return sscreen->info.gfx_level >= GFX10;
193
194 case PIPE_CAP_GRAPHICS:
195 return sscreen->info.has_graphics;
196
197 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
198 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
199
200 case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
201 return sscreen->info.has_tmz_support;
202
203 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
204 return SI_MAP_BUFFER_ALIGNMENT;
205
206 case PIPE_CAP_MAX_VERTEX_BUFFERS:
207 return SI_MAX_ATTRIBS;
208
209 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
210 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
211 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
212 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
213 case PIPE_CAP_MAX_VERTEX_STREAMS:
214 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
215 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
216 return 4;
217
218 case PIPE_CAP_GLSL_FEATURE_LEVEL:
219 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
220 return 460;
221
222 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
223 /* Optimal number for good TexSubImage performance on Polaris10. */
224 return 64 * 1024 * 1024;
225
226 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
227 return 4096 * 1024;
228
229 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: {
230 unsigned max_texels =
231 pscreen->get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT);
232
233 /* FYI, BUF_RSRC_WORD2.NUM_RECORDS field limit is UINT32_MAX. */
234
235 /* Gfx8 and older use the size in bytes for bounds checking, and the max element size
236 * is 16B. Gfx9 and newer use the VGPR index for bounds checking.
237 */
238 if (sscreen->info.gfx_level <= GFX8)
239 max_texels = MIN2(max_texels, UINT32_MAX / 16);
240 else
241 /* Gallium has a limitation that it can only bind UINT32_MAX bytes, not texels.
242 * TODO: Remove this after the gallium interface is changed. */
243 max_texels = MIN2(max_texels, UINT32_MAX / 16);
244
245 return max_texels;
246 }
247
248 case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
249 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: {
250 /* Return 1/4th of the heap size as the maximum because the max size is not practically
251 * allocatable. Also, this can only return UINT32_MAX at most.
252 */
253 unsigned max_size = MIN2((sscreen->info.max_heap_size_kb * 1024ull) / 4, UINT32_MAX);
254
255 /* Allow max 512 MB to pass CTS with a 32-bit build. */
256 if (sizeof(void*) == 4)
257 max_size = MIN2(max_size, 512 * 1024 * 1024);
258
259 return max_size;
260 }
261
262 case PIPE_CAP_MAX_TEXTURE_MB:
263 /* Allow 1/4th of the heap size. */
264 return sscreen->info.max_heap_size_kb / 1024 / 4;
265
266 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
267 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
269 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
270 return 0;
271
272 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
273 return enable_sparse ? RADEON_SPARSE_PAGE_SIZE : 0;
274
275 case PIPE_CAP_UMA:
276 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
277 return 0;
278
279 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
280 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 22))
281 return 0;
282 return PIPE_CONTEXT_PRIORITY_LOW |
283 PIPE_CONTEXT_PRIORITY_MEDIUM |
284 PIPE_CONTEXT_PRIORITY_HIGH;
285
286 case PIPE_CAP_FENCE_SIGNAL:
287 return sscreen->info.has_syncobj;
288
289 case PIPE_CAP_CONSTBUF0_FLAGS:
290 return SI_RESOURCE_FLAG_32BIT;
291
292 case PIPE_CAP_NATIVE_FENCE_FD:
293 return sscreen->info.has_fence_to_handle;
294
295 case PIPE_CAP_DRAW_PARAMETERS:
296 case PIPE_CAP_MULTI_DRAW_INDIRECT:
297 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
298 return sscreen->has_draw_indirect_multi;
299
300 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
301 return 30;
302
303 case PIPE_CAP_MAX_VARYINGS:
304 return 32;
305
306 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
307 return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
308
309 /* Stream output. */
310 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
311 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
312 return 32 * 4;
313
314 /* Geometry shader output. */
315 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
316 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
317 * gfx8 and earlier can do 1024.
318 */
319 return 256;
320 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
321 return 4095;
322 case PIPE_CAP_MAX_GS_INVOCATIONS:
323 /* Even though the hw supports more, we officially wanna expose only 32. */
324 return 32;
325
326 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
327 return 2048;
328
329 /* Texturing. */
330 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
331 return 16384;
332 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
333 if (!sscreen->info.has_3d_cube_border_color_mipmap)
334 return 0;
335 return 15; /* 16384 */
336 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
337 if (!sscreen->info.has_3d_cube_border_color_mipmap)
338 return 0;
339 if (sscreen->info.gfx_level >= GFX10)
340 return 14;
341 /* textures support 8192, but layered rendering supports 2048 */
342 return 12;
343 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
344 if (sscreen->info.gfx_level >= GFX10)
345 return 8192;
346 /* textures support 8192, but layered rendering supports 2048 */
347 return 2048;
348
349 /* Sparse texture */
350 case PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE:
351 return enable_sparse ?
352 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_2D_SIZE) : 0;
353 case PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE:
354 return enable_sparse ?
355 (1 << (si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_3D_LEVELS) - 1)) : 0;
356 case PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS:
357 return enable_sparse ?
358 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS) : 0;
359 case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
360 case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
361 case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
362 return enable_sparse;
363
364 /* Viewports and render targets. */
365 case PIPE_CAP_MAX_VIEWPORTS:
366 return SI_MAX_VIEWPORTS;
367 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
368 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
369 case PIPE_CAP_MAX_RENDER_TARGETS:
370 return 8;
371 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
372 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
373
374 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
375 case PIPE_CAP_MIN_TEXEL_OFFSET:
376 return -32;
377
378 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
379 case PIPE_CAP_MAX_TEXEL_OFFSET:
380 return 31;
381
382 case PIPE_CAP_ENDIANNESS:
383 return PIPE_ENDIAN_LITTLE;
384
385 case PIPE_CAP_VENDOR_ID:
386 return ATI_VENDOR_ID;
387 case PIPE_CAP_DEVICE_ID:
388 return sscreen->info.pci_id;
389 case PIPE_CAP_VIDEO_MEMORY:
390 return sscreen->info.vram_size_kb >> 10;
391 case PIPE_CAP_PCI_GROUP:
392 return sscreen->info.pci_domain;
393 case PIPE_CAP_PCI_BUS:
394 return sscreen->info.pci_bus;
395 case PIPE_CAP_PCI_DEVICE:
396 return sscreen->info.pci_dev;
397 case PIPE_CAP_PCI_FUNCTION:
398 return sscreen->info.pci_func;
399
400 default:
401 return u_pipe_screen_get_param_defaults(pscreen, param);
402 }
403 }
404
si_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)405 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
406 {
407 switch (param) {
408 case PIPE_CAPF_MIN_LINE_WIDTH:
409 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
410 return 1; /* due to axis-aligned end caps at line width 1 */
411 case PIPE_CAPF_MIN_POINT_SIZE:
412 case PIPE_CAPF_MIN_POINT_SIZE_AA:
413 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
414 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
415 return 1.0 / 8.0; /* due to the register field precision */
416 case PIPE_CAPF_MAX_LINE_WIDTH:
417 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
418 /* This depends on the quant mode, though the precise interactions
419 * are unknown. */
420 return 2048;
421 case PIPE_CAPF_MAX_POINT_SIZE:
422 case PIPE_CAPF_MAX_POINT_SIZE_AA:
423 return SI_MAX_POINT_SIZE;
424 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
425 return 16.0f;
426 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
427 return 16.0f;
428 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
429 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
430 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
431 return 0.0f;
432 }
433 return 0.0f;
434 }
435
si_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)436 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
437 enum pipe_shader_cap param)
438 {
439 struct si_screen *sscreen = (struct si_screen *)pscreen;
440
441 switch (param) {
442 /* Shader limits. */
443 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
444 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
445 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
446 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
447 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
448 return 16384;
449 case PIPE_SHADER_CAP_MAX_INPUTS:
450 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
451 case PIPE_SHADER_CAP_MAX_OUTPUTS:
452 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
453 case PIPE_SHADER_CAP_MAX_TEMPS:
454 return 256; /* Max native temporaries. */
455 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
456 return 1 << 26; /* 64 MB */
457 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
458 return SI_NUM_CONST_BUFFERS;
459 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
460 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
461 return SI_NUM_SAMPLERS;
462 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
463 return SI_NUM_SHADER_BUFFERS;
464 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
465 return SI_NUM_IMAGES;
466 case PIPE_SHADER_CAP_PREFERRED_IR:
467 return PIPE_SHADER_IR_NIR;
468
469 case PIPE_SHADER_CAP_SUPPORTED_IRS:
470 if (shader == PIPE_SHADER_COMPUTE) {
471 return (1 << PIPE_SHADER_IR_NATIVE) |
472 (1 << PIPE_SHADER_IR_NIR) |
473 (1 << PIPE_SHADER_IR_TGSI);
474 }
475 return (1 << PIPE_SHADER_IR_TGSI) |
476 (1 << PIPE_SHADER_IR_NIR);
477
478 /* Supported boolean features. */
479 case PIPE_SHADER_CAP_CONT_SUPPORTED:
480 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
481 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
482 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
483 case PIPE_SHADER_CAP_INTEGERS:
484 case PIPE_SHADER_CAP_INT64_ATOMICS:
485 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
486 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
487 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
488 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
489 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
490 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
491 return 1;
492
493 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
494 /* We need f16c for fast FP16 conversions in glUniform. */
495 if (!util_get_cpu_caps()->has_f16c)
496 return 0;
497 FALLTHROUGH;
498 case PIPE_SHADER_CAP_FP16:
499 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
500 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
501 return sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
502
503 /* Unsupported boolean features. */
504 case PIPE_SHADER_CAP_INT16:
505 case PIPE_SHADER_CAP_SUBROUTINES:
506 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
507 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
508 return 0;
509 }
510 return 0;
511 }
512
si_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)513 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
514 enum pipe_shader_type shader)
515 {
516 struct si_screen *sscreen = (struct si_screen *)screen;
517
518 assert(ir == PIPE_SHADER_IR_NIR);
519 return &sscreen->nir_options;
520 }
521
si_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)522 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
523 {
524 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
525 }
526
si_get_device_uuid(struct pipe_screen * pscreen,char * uuid)527 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
528 {
529 struct si_screen *sscreen = (struct si_screen *)pscreen;
530
531 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
532 }
533
si_get_name(struct pipe_screen * pscreen)534 static const char *si_get_name(struct pipe_screen *pscreen)
535 {
536 struct si_screen *sscreen = (struct si_screen *)pscreen;
537
538 return sscreen->renderer_string;
539 }
540
si_get_video_param_no_video_hw(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)541 static int si_get_video_param_no_video_hw(struct pipe_screen *screen, enum pipe_video_profile profile,
542 enum pipe_video_entrypoint entrypoint,
543 enum pipe_video_cap param)
544 {
545 switch (param) {
546 case PIPE_VIDEO_CAP_SUPPORTED:
547 return vl_profile_supported(screen, profile, entrypoint);
548 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
549 return 1;
550 case PIPE_VIDEO_CAP_MAX_WIDTH:
551 case PIPE_VIDEO_CAP_MAX_HEIGHT:
552 return vl_video_buffer_max_size(screen);
553 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
554 return PIPE_FORMAT_NV12;
555 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
556 return false;
557 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
558 return false;
559 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
560 return true;
561 case PIPE_VIDEO_CAP_MAX_LEVEL:
562 return vl_level_supported(screen, profile);
563 default:
564 return 0;
565 }
566 }
567
si_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)568 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
569 enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
570 {
571 struct si_screen *sscreen = (struct si_screen *)screen;
572 enum pipe_video_format codec = u_reduce_video_profile(profile);
573
574 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
575 if (!(sscreen->info.ip[AMD_IP_VCE].num_queues ||
576 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues ||
577 sscreen->info.ip[AMD_IP_VCN_ENC].num_queues))
578 return 0;
579
580 switch (param) {
581 case PIPE_VIDEO_CAP_SUPPORTED:
582 return (
583 (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
584 (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
585 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
586 (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
587 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
588 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
589 return 1;
590 case PIPE_VIDEO_CAP_MAX_WIDTH:
591 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
592 sscreen->info.enc_caps.codec_info[codec - 1].valid)
593 return sscreen->info.enc_caps.codec_info[codec - 1].max_width;
594 else
595 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
596 case PIPE_VIDEO_CAP_MAX_HEIGHT:
597 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
598 sscreen->info.enc_caps.codec_info[codec - 1].valid)
599 return sscreen->info.enc_caps.codec_info[codec - 1].max_height;
600 else
601 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
602 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
603 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
604 return PIPE_FORMAT_P010;
605 else
606 return PIPE_FORMAT_NV12;
607 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
608 return false;
609 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
610 return false;
611 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
612 return true;
613 case PIPE_VIDEO_CAP_STACKED_FRAMES:
614 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
615 case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
616 if (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
617 sscreen->info.family >= CHIP_RAVEN)
618 return 4;
619 else
620 return 0;
621 default:
622 return 0;
623 }
624 }
625
626 switch (param) {
627 case PIPE_VIDEO_CAP_SUPPORTED:
628 if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
629 sscreen->info.family >= CHIP_NAVI24)
630 return false;
631 if (codec != PIPE_VIDEO_FORMAT_JPEG &&
632 !(sscreen->info.ip[AMD_IP_UVD].num_queues ||
633 sscreen->info.has_video_hw.vcn_decode))
634 return false;
635
636 switch (codec) {
637 case PIPE_VIDEO_FORMAT_MPEG12:
638 if (sscreen->info.gfx_level >= GFX11)
639 return false;
640 else
641 return profile != PIPE_VIDEO_PROFILE_MPEG1;
642 case PIPE_VIDEO_FORMAT_MPEG4:
643 if (sscreen->info.gfx_level >= GFX11)
644 return false;
645 else
646 return true;
647 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
648 if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
649 sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
650 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
651 return false;
652 }
653 return true;
654 case PIPE_VIDEO_FORMAT_VC1:
655 if (sscreen->info.gfx_level >= GFX11)
656 return false;
657 else
658 return true;
659 case PIPE_VIDEO_FORMAT_HEVC:
660 /* Carrizo only supports HEVC Main */
661 if (sscreen->info.family >= CHIP_STONEY)
662 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
663 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
664 else if (sscreen->info.family >= CHIP_CARRIZO)
665 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
666 return false;
667 case PIPE_VIDEO_FORMAT_JPEG:
668 if (sscreen->info.family >= CHIP_RAVEN) {
669 if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues)
670 return false;
671 else
672 return true;
673 }
674 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
675 return false;
676 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
677 RVID_ERR("No MJPEG support for the kernel version\n");
678 return false;
679 }
680 return true;
681 case PIPE_VIDEO_FORMAT_VP9:
682 if (sscreen->info.family < CHIP_RAVEN)
683 return false;
684 return true;
685 case PIPE_VIDEO_FORMAT_AV1:
686 if (sscreen->info.family < CHIP_NAVI21)
687 return false;
688 return true;
689 default:
690 return false;
691 }
692 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
693 return 1;
694 case PIPE_VIDEO_CAP_MAX_WIDTH:
695 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
696 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
697 return sscreen->info.dec_caps.codec_info[codec - 1].max_width;
698 } else {
699 switch (codec) {
700 case PIPE_VIDEO_FORMAT_HEVC:
701 case PIPE_VIDEO_FORMAT_VP9:
702 case PIPE_VIDEO_FORMAT_AV1:
703 return (sscreen->info.family < CHIP_RENOIR) ?
704 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
705 default:
706 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
707 }
708 }
709 case PIPE_VIDEO_CAP_MAX_HEIGHT:
710 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
711 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
712 return sscreen->info.dec_caps.codec_info[codec - 1].max_height;
713 } else {
714 switch (codec) {
715 case PIPE_VIDEO_FORMAT_HEVC:
716 case PIPE_VIDEO_FORMAT_VP9:
717 case PIPE_VIDEO_FORMAT_AV1:
718 return (sscreen->info.family < CHIP_RENOIR) ?
719 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
720 default:
721 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
722 }
723 }
724 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
725 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
726 return PIPE_FORMAT_P010;
727 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
728 return PIPE_FORMAT_P010;
729 else
730 return PIPE_FORMAT_NV12;
731
732 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
733 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
734 enum pipe_video_format format = u_reduce_video_profile(profile);
735
736 if (format >= PIPE_VIDEO_FORMAT_HEVC)
737 return false;
738 return true;
739 }
740 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
741 return true;
742 case PIPE_VIDEO_CAP_MAX_LEVEL:
743 if ((profile == PIPE_VIDEO_PROFILE_MPEG2_SIMPLE ||
744 profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN ||
745 profile == PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE ||
746 profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) &&
747 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
748 return sscreen->info.dec_caps.codec_info[codec - 1].max_level;
749 } else {
750 switch (profile) {
751 case PIPE_VIDEO_PROFILE_MPEG1:
752 return 0;
753 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
754 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
755 return 3;
756 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
757 return 3;
758 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
759 return 5;
760 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
761 return 1;
762 case PIPE_VIDEO_PROFILE_VC1_MAIN:
763 return 2;
764 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
765 return 4;
766 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
767 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
768 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
769 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
770 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
771 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
772 return 186;
773 default:
774 return 0;
775 }
776 }
777 default:
778 return 0;
779 }
780 }
781
si_vid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)782 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
783 enum pipe_video_profile profile,
784 enum pipe_video_entrypoint entrypoint)
785 {
786 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
787 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
788 return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
789 (format == PIPE_FORMAT_P016);
790
791 /* Vp9 profile 2 supports 10 bit decoding using P016 */
792 if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
793 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
794
795 /* we can only handle this one with UVD */
796 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
797 return format == PIPE_FORMAT_NV12;
798
799 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
800 }
801
get_max_threads_per_block(struct si_screen * screen,enum pipe_shader_ir ir_type)802 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
803 {
804 if (ir_type == PIPE_SHADER_IR_NATIVE)
805 return 256;
806
807 /* LLVM only supports 1024 threads per block. */
808 return 1024;
809 }
810
si_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)811 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
812 enum pipe_compute_cap param, void *ret)
813 {
814 struct si_screen *sscreen = (struct si_screen *)screen;
815
816 // TODO: select these params by asic
817 switch (param) {
818 case PIPE_COMPUTE_CAP_IR_TARGET: {
819 const char *gpu, *triple;
820
821 triple = "amdgcn-mesa-mesa3d";
822 gpu = ac_get_llvm_processor_name(sscreen->info.family);
823 if (ret) {
824 sprintf(ret, "%s-%s", gpu, triple);
825 }
826 /* +2 for dash and terminating NIL byte */
827 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
828 }
829 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
830 if (ret) {
831 uint64_t *grid_dimension = ret;
832 grid_dimension[0] = 3;
833 }
834 return 1 * sizeof(uint64_t);
835
836 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
837 if (ret) {
838 uint64_t *grid_size = ret;
839 grid_size[0] = UINT32_MAX;
840 grid_size[1] = UINT32_MAX;
841 grid_size[2] = UINT32_MAX;
842 }
843 return 3 * sizeof(uint64_t);
844
845 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
846 if (ret) {
847 uint64_t *block_size = ret;
848 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
849 block_size[0] = threads_per_block;
850 block_size[1] = threads_per_block;
851 block_size[2] = threads_per_block;
852 }
853 return 3 * sizeof(uint64_t);
854
855 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
856 if (ret) {
857 uint64_t *max_threads_per_block = ret;
858 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
859 }
860 return sizeof(uint64_t);
861 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
862 if (ret) {
863 uint32_t *address_bits = ret;
864 address_bits[0] = 64;
865 }
866 return 1 * sizeof(uint32_t);
867
868 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
869 if (ret) {
870 uint64_t *max_global_size = ret;
871 uint64_t max_mem_alloc_size;
872
873 si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
874 &max_mem_alloc_size);
875
876 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
877 * 1/4 of the MAX_GLOBAL_SIZE. Since the
878 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
879 * make sure we never report more than
880 * 4 * MAX_MEM_ALLOC_SIZE.
881 */
882 *max_global_size =
883 MIN2(4 * max_mem_alloc_size, sscreen->info.max_heap_size_kb * 1024ull);
884 }
885 return sizeof(uint64_t);
886
887 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
888 if (ret) {
889 uint64_t *max_local_size = ret;
890 /* Value reported by the closed source driver. */
891 if (sscreen->info.gfx_level == GFX6)
892 *max_local_size = 32 * 1024;
893 else
894 *max_local_size = 64 * 1024;
895 }
896 return sizeof(uint64_t);
897
898 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
899 if (ret) {
900 uint64_t *max_input_size = ret;
901 /* Value reported by the closed source driver. */
902 *max_input_size = 1024;
903 }
904 return sizeof(uint64_t);
905
906 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
907 if (ret) {
908 uint64_t *max_mem_alloc_size = ret;
909
910 /* Return 1/4 of the heap size as the maximum because the max size is not practically
911 * allocatable.
912 */
913 *max_mem_alloc_size = (sscreen->info.max_heap_size_kb / 4) * 1024ull;
914 }
915 return sizeof(uint64_t);
916
917 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
918 if (ret) {
919 uint32_t *max_clock_frequency = ret;
920 *max_clock_frequency = sscreen->info.max_gpu_freq_mhz;
921 }
922 return sizeof(uint32_t);
923
924 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
925 if (ret) {
926 uint32_t *max_compute_units = ret;
927 *max_compute_units = sscreen->info.num_cu;
928 }
929 return sizeof(uint32_t);
930
931 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
932 if (ret) {
933 uint32_t *images_supported = ret;
934 *images_supported = 0;
935 }
936 return sizeof(uint32_t);
937 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
938 break; /* unused */
939 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
940 if (ret) {
941 uint32_t *subgroup_size = ret;
942 *subgroup_size = si_determine_wave_size(sscreen, NULL);
943 }
944 return sizeof(uint32_t);
945 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
946 if (ret) {
947 uint64_t *max_variable_threads_per_block = ret;
948 if (ir_type == PIPE_SHADER_IR_NATIVE)
949 *max_variable_threads_per_block = 0;
950 else
951 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
952 }
953 return sizeof(uint64_t);
954 }
955
956 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
957 return 0;
958 }
959
si_get_timestamp(struct pipe_screen * screen)960 static uint64_t si_get_timestamp(struct pipe_screen *screen)
961 {
962 struct si_screen *sscreen = (struct si_screen *)screen;
963
964 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
965 sscreen->info.clock_crystal_freq;
966 }
967
si_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)968 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
969 {
970 struct si_screen *sscreen = (struct si_screen *)screen;
971 struct radeon_winsys *ws = sscreen->ws;
972 unsigned vram_usage, gtt_usage;
973
974 info->total_device_memory = sscreen->info.vram_size_kb;
975 info->total_staging_memory = sscreen->info.gart_size_kb;
976
977 /* The real TTM memory usage is somewhat random, because:
978 *
979 * 1) TTM delays freeing memory, because it can only free it after
980 * fences expire.
981 *
982 * 2) The memory usage can be really low if big VRAM evictions are
983 * taking place, but the real usage is well above the size of VRAM.
984 *
985 * Instead, return statistics of this process.
986 */
987 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
988 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
989
990 info->avail_device_memory =
991 vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
992 info->avail_staging_memory =
993 gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
994
995 info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
996
997 if (sscreen->info.is_amdgpu)
998 info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
999 else
1000 /* Just return the number of evicted 64KB pages. */
1001 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1002 }
1003
si_get_disk_shader_cache(struct pipe_screen * pscreen)1004 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
1005 {
1006 struct si_screen *sscreen = (struct si_screen *)pscreen;
1007
1008 return sscreen->disk_shader_cache;
1009 }
1010
si_init_renderer_string(struct si_screen * sscreen)1011 static void si_init_renderer_string(struct si_screen *sscreen)
1012 {
1013 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
1014 struct utsname uname_data;
1015
1016 snprintf(first_name, sizeof(first_name), "%s",
1017 sscreen->info.marketing_name ? sscreen->info.marketing_name : sscreen->info.name);
1018 snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.lowercase_name);
1019
1020 if (uname(&uname_data) == 0)
1021 snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
1022
1023 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
1024 "%s (%sLLVM " MESA_LLVM_VERSION_STRING ", DRM %i.%i%s)", first_name, second_name,
1025 sscreen->info.drm_major, sscreen->info.drm_minor, kernel_version);
1026 }
1027
si_init_screen_get_functions(struct si_screen * sscreen)1028 void si_init_screen_get_functions(struct si_screen *sscreen)
1029 {
1030 sscreen->b.get_name = si_get_name;
1031 sscreen->b.get_vendor = si_get_vendor;
1032 sscreen->b.get_device_vendor = si_get_device_vendor;
1033 sscreen->b.get_param = si_get_param;
1034 sscreen->b.get_paramf = si_get_paramf;
1035 sscreen->b.get_compute_param = si_get_compute_param;
1036 sscreen->b.get_timestamp = si_get_timestamp;
1037 sscreen->b.get_shader_param = si_get_shader_param;
1038 sscreen->b.get_compiler_options = si_get_compiler_options;
1039 sscreen->b.get_device_uuid = si_get_device_uuid;
1040 sscreen->b.get_driver_uuid = si_get_driver_uuid;
1041 sscreen->b.query_memory_info = si_query_memory_info;
1042 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1043
1044 if (sscreen->info.ip[AMD_IP_UVD].num_queues || sscreen->info.has_video_hw.vcn_decode ||
1045 sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
1046 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) {
1047 sscreen->b.get_video_param = si_get_video_param;
1048 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1049 } else {
1050 sscreen->b.get_video_param = si_get_video_param_no_video_hw;
1051 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1052 }
1053
1054 si_init_renderer_string(sscreen);
1055
1056 /* fma32 is too slow for gpu < gfx9, so force it only when gpu >= gfx9 */
1057 bool force_fma32 =
1058 sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32;
1059
1060 const struct nir_shader_compiler_options nir_options = {
1061 .vertex_id_zero_based = true,
1062 .lower_scmp = true,
1063 .lower_flrp16 = true,
1064 .lower_flrp32 = true,
1065 .lower_flrp64 = true,
1066 .lower_fsat = true,
1067 .lower_fdiv = true,
1068 .lower_bitfield_insert_to_bitfield_select = true,
1069 .lower_bitfield_extract = true,
1070 /* |---------------------------------- Performance & Availability --------------------------------|
1071 * |MAD/MAC/MADAK/MADMK|MAD_LEGACY|MAC_LEGACY| FMA |FMAC/FMAAK/FMAMK|FMA_LEGACY|PK_FMA_F16,|Best choice
1072 * Arch | F32,F16,F64 | F32,F16 | F32,F16 |F32,F16,F64 | F32,F16 | F32,F16 |PK_FMAC_F16|F16,F32,F64
1073 * ------------------------------------------------------------------------------------------------------------------
1074 * gfx6,7 | 1 , - , - | 1 , - | 1 , - |1/4, - ,1/16| - , - | - , - | - , - | - ,MAD,FMA
1075 * gfx8 | 1 , 1 , - | 1 , - | - , - |1/4, 1 ,1/16| - , - | - , - | - , - |MAD,MAD,FMA
1076 * gfx9 | 1 ,1|0, - | 1 , - | - , - | 1 , 1 ,1/16| 0|1, - | - , 1 | 2 , - |FMA,MAD,FMA
1077 * gfx10 | 1 , - , - | 1 , - | 1 , - | 1 , 1 ,1/16| 1 , 1 | - , - | 2 , 2 |FMA,MAD,FMA
1078 * gfx10.3| - , - , - | - , - | - , - | 1 , 1 ,1/16| 1 , 1 | 1 , - | 2 , 2 | all FMA
1079 *
1080 * Tahiti, Hawaii, Carrizo, Vega20: FMA_F32 is full rate, FMA_F64 is 1/4
1081 * gfx9 supports MAD_F16 only on Vega10, Raven, Raven2, Renoir.
1082 * gfx9 supports FMAC_F32 only on Vega20, but doesn't support FMAAK and FMAMK.
1083 *
1084 * gfx8 prefers MAD for F16 because of MAC/MADAK/MADMK.
1085 * gfx9 and newer prefer FMA for F16 because of the packed instruction.
1086 * gfx10 and older prefer MAD for F32 because of the legacy instruction.
1087 */
1088 .lower_ffma16 = sscreen->info.gfx_level < GFX9,
1089 .lower_ffma32 = sscreen->info.gfx_level < GFX10_3 && !force_fma32,
1090 .lower_ffma64 = false,
1091 .fuse_ffma16 = sscreen->info.gfx_level >= GFX9,
1092 .fuse_ffma32 = sscreen->info.gfx_level >= GFX10_3 || force_fma32,
1093 .fuse_ffma64 = true,
1094 .lower_fmod = true,
1095 .lower_pack_snorm_4x8 = true,
1096 .lower_pack_unorm_4x8 = true,
1097 .lower_unpack_snorm_2x16 = true,
1098 .lower_unpack_snorm_4x8 = true,
1099 .lower_unpack_unorm_2x16 = true,
1100 .lower_unpack_unorm_4x8 = true,
1101 .lower_extract_byte = true,
1102 .lower_extract_word = true,
1103 .lower_insert_byte = true,
1104 .lower_insert_word = true,
1105 .lower_rotate = true,
1106 .lower_to_scalar = true,
1107 .lower_int64_options = nir_lower_imul_2x32_64,
1108 .has_sdot_4x8 = sscreen->info.has_accelerated_dot_product,
1109 .has_udot_4x8 = sscreen->info.has_accelerated_dot_product,
1110 .has_dot_2x16 = sscreen->info.has_accelerated_dot_product,
1111 .optimize_sample_mask_in = true,
1112 .max_unroll_iterations = LLVM_VERSION_MAJOR >= 13 ? 128 : 32,
1113 .max_unroll_iterations_aggressive = LLVM_VERSION_MAJOR >= 13 ? 128 : 32,
1114 .use_interpolated_input_intrinsics = true,
1115 .lower_uniforms_to_ubo = true,
1116 .support_16bit_alu = sscreen->info.gfx_level >= GFX8,
1117 .vectorize_vec2_16bit = sscreen->info.has_packed_math_16bit,
1118 .pack_varying_options =
1119 nir_pack_varying_interp_mode_none |
1120 nir_pack_varying_interp_mode_smooth |
1121 nir_pack_varying_interp_mode_noperspective |
1122 nir_pack_varying_interp_loc_center |
1123 nir_pack_varying_interp_loc_sample |
1124 nir_pack_varying_interp_loc_centroid,
1125 .lower_io_variables = true,
1126 .lower_fs_color_inputs = true,
1127 /* HW supports indirect indexing for: | Enabled in driver
1128 * -------------------------------------------------------
1129 * TCS inputs | Yes
1130 * TES inputs | Yes
1131 * GS inputs | No
1132 * -------------------------------------------------------
1133 * VS outputs before TCS | No
1134 * TCS outputs | Yes
1135 * VS/TES outputs before GS | No
1136 */
1137 .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
1138 BITFIELD_BIT(MESA_SHADER_TESS_EVAL),
1139 .support_indirect_outputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL),
1140 };
1141 sscreen->nir_options = nir_options;
1142 }
1143