1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // Declares a Simulator for S390 instructions if we are not generating a native
6 // S390 binary. This Simulator allows us to run and debug S390 code generation
7 // on regular desktop machines.
8 // V8 calls into generated code via the GeneratedCode wrapper,
9 // which will start execution in the Simulator or forwards to the real entry
10 // on a S390 hardware platform.
11
12 #ifndef V8_EXECUTION_S390_SIMULATOR_S390_H_
13 #define V8_EXECUTION_S390_SIMULATOR_S390_H_
14
15 // globals.h defines USE_SIMULATOR.
16 #include "src/common/globals.h"
17
18 #if defined(USE_SIMULATOR)
19 // Running with a simulator.
20
21 #include "src/base/hashmap.h"
22 #include "src/codegen/assembler.h"
23 #include "src/codegen/s390/constants-s390.h"
24 #include "src/execution/simulator-base.h"
25 #include "src/utils/allocation.h"
26
27 namespace v8 {
28 namespace internal {
29
30 class CachePage {
31 public:
32 static const int LINE_VALID = 0;
33 static const int LINE_INVALID = 1;
34
35 static const int kPageShift = 12;
36 static const int kPageSize = 1 << kPageShift;
37 static const int kPageMask = kPageSize - 1;
38 static const int kLineShift = 2; // The cache line is only 4 bytes right now.
39 static const int kLineLength = 1 << kLineShift;
40 static const int kLineMask = kLineLength - 1;
41
CachePage()42 CachePage() { memset(&validity_map_, LINE_INVALID, sizeof(validity_map_)); }
43
ValidityByte(int offset)44 char* ValidityByte(int offset) {
45 return &validity_map_[offset >> kLineShift];
46 }
47
CachedData(int offset)48 char* CachedData(int offset) { return &data_[offset]; }
49
50 private:
51 char data_[kPageSize]; // The cached data.
52 static const int kValidityMapSize = kPageSize >> kLineShift;
53 char validity_map_[kValidityMapSize]; // One byte per line.
54 };
55
56 template <class T>
ComputeRounding(T a,int mode)57 static T ComputeRounding(T a, int mode) {
58 switch (mode) {
59 case ROUND_TO_NEAREST_AWAY_FROM_0:
60 return std::round(a);
61 case ROUND_TO_NEAREST_TO_EVEN:
62 return std::nearbyint(a);
63 case ROUND_TOWARD_0:
64 return std::trunc(a);
65 case ROUND_TOWARD_POS_INF:
66 return std::ceil(a);
67 case ROUND_TOWARD_NEG_INF:
68 return std::floor(a);
69 default:
70 UNIMPLEMENTED();
71 }
72 return 0;
73 }
74
75 class Simulator : public SimulatorBase {
76 public:
77 friend class S390Debugger;
78 enum Register {
79 no_reg = -1,
80 r0 = 0,
81 r1 = 1,
82 r2 = 2,
83 r3 = 3,
84 r4 = 4,
85 r5 = 5,
86 r6 = 6,
87 r7 = 7,
88 r8 = 8,
89 r9 = 9,
90 r10 = 10,
91 r11 = 11,
92 r12 = 12,
93 r13 = 13,
94 r14 = 14,
95 r15 = 15,
96 fp = r11,
97 ip = r12,
98 cp = r13,
99 ra = r14,
100 sp = r15, // name aliases
101 kNumGPRs = 16,
102 d0 = 0,
103 d1,
104 d2,
105 d3,
106 d4,
107 d5,
108 d6,
109 d7,
110 d8,
111 d9,
112 d10,
113 d11,
114 d12,
115 d13,
116 d14,
117 d15,
118 kNumFPRs = 16
119 };
120
121 explicit Simulator(Isolate* isolate);
122 ~Simulator();
123
124 // The currently executing Simulator instance. Potentially there can be one
125 // for each native thread.
126 static Simulator* current(v8::internal::Isolate* isolate);
127
128 // Accessors for register state.
129 void set_register(int reg, uint64_t value);
130 const uint64_t& get_register(int reg) const;
131 uint64_t& get_register(int reg);
132 template <typename T>
133 T get_low_register(int reg) const;
134 template <typename T>
135 T get_high_register(int reg) const;
136 void set_low_register(int reg, uint32_t value);
137 void set_high_register(int reg, uint32_t value);
138
139 double get_double_from_register_pair(int reg);
140
141 // Unlike Integer values, Floating Point values are located on the left most
142 // side of a native 64 bit register. As FP registers are a subset of vector
143 // registers, 64 and 32 bit FP values need to be located on first lane (lane
144 // number 0) of a vector register.
145 template <class T>
get_fpr(int dreg)146 T get_fpr(int dreg) {
147 DCHECK(dreg >= 0 && dreg < kNumFPRs);
148 return get_simd_register_by_lane<T>(dreg, 0);
149 }
150
151 template <class T>
set_fpr(int dreg,const T val)152 void set_fpr(int dreg, const T val) {
153 DCHECK(dreg >= 0 && dreg < kNumFPRs);
154 set_simd_register_by_lane<T>(dreg, 0, val);
155 }
156
157 // Special case of set_register and get_register to access the raw PC value.
158 void set_pc(intptr_t value);
159 intptr_t get_pc() const;
160
get_sp()161 Address get_sp() const { return static_cast<Address>(get_register(sp)); }
162
163 // Accessor to the internal simulator stack area.
164 uintptr_t StackLimit(uintptr_t c_limit) const;
165
166 // Executes S390 instructions until the PC reaches end_sim_pc.
167 void Execute();
168
169 template <typename Return, typename... Args>
Call(Address entry,Args...args)170 Return Call(Address entry, Args... args) {
171 return VariadicCall<Return>(this, &Simulator::CallImpl, entry, args...);
172 }
173
174 // Alternative: call a 2-argument double function.
175 void CallFP(Address entry, double d0, double d1);
176 int32_t CallFPReturnsInt(Address entry, double d0, double d1);
177 double CallFPReturnsDouble(Address entry, double d0, double d1);
178
179 // Push an address onto the JS stack.
180 uintptr_t PushAddress(uintptr_t address);
181
182 // Pop an address from the JS stack.
183 uintptr_t PopAddress();
184
185 // Debugger input.
186 void set_last_debugger_input(char* input);
last_debugger_input()187 char* last_debugger_input() { return last_debugger_input_; }
188
189 // Redirection support.
190 static void SetRedirectInstruction(Instruction* instruction);
191
192 // ICache checking.
193 static bool ICacheMatch(void* one, void* two);
194 static void FlushICache(base::CustomMatcherHashMap* i_cache, void* start,
195 size_t size);
196
197 // Returns true if pc register contains one of the 'special_values' defined
198 // below (bad_lr, end_sim_pc).
199 bool has_bad_pc() const;
200
201 enum special_values {
202 // Known bad pc value to ensure that the simulator does not execute
203 // without being properly setup.
204 bad_lr = -1,
205 // A pc value used to signal the simulator to stop execution. Generally
206 // the lr is set to this value on transition from native C code to
207 // simulated execution, so that the simulator can "return" to the native
208 // C code.
209 end_sim_pc = -2
210 };
211
212 intptr_t CallImpl(Address entry, int argument_count,
213 const intptr_t* arguments);
214
215 // Unsupported instructions use Format to print an error and stop execution.
216 void Format(Instruction* instr, const char* format);
217
218 // Helper functions to set the conditional flags in the architecture state.
219 bool CarryFrom(int32_t left, int32_t right, int32_t carry = 0);
220 bool BorrowFrom(int32_t left, int32_t right);
221 template <typename T1>
222 inline bool OverflowFromSigned(T1 alu_out, T1 left, T1 right, bool addition);
223
224 // Helper functions to decode common "addressing" modes
225 int32_t GetShiftRm(Instruction* instr, bool* carry_out);
226 int32_t GetImm(Instruction* instr, bool* carry_out);
227 void ProcessPUW(Instruction* instr, int num_regs, int operand_size,
228 intptr_t* start_address, intptr_t* end_address);
229 void HandleRList(Instruction* instr, bool load);
230 void HandleVList(Instruction* inst);
231 void SoftwareInterrupt(Instruction* instr);
232 void DebugAtNextPC();
233
234 // Stop helper functions.
235 inline bool isStopInstruction(Instruction* instr);
236 inline bool isWatchedStop(uint32_t bkpt_code);
237 inline bool isEnabledStop(uint32_t bkpt_code);
238 inline void EnableStop(uint32_t bkpt_code);
239 inline void DisableStop(uint32_t bkpt_code);
240 inline void IncreaseStopCounter(uint32_t bkpt_code);
241 void PrintStopInfo(uint32_t code);
242
243 // Byte Reverse
__builtin_bswap128(__uint128_t v)244 static inline __uint128_t __builtin_bswap128(__uint128_t v) {
245 union {
246 uint64_t u64[2];
247 __uint128_t u128;
248 } res, val;
249 val.u128 = v;
250 res.u64[0] = __builtin_bswap64(val.u64[1]);
251 res.u64[1] = __builtin_bswap64(val.u64[0]);
252 return res.u128;
253 }
254
255 template <class T>
ByteReverse(T val)256 static inline T ByteReverse(T val) {
257 constexpr int size = sizeof(T);
258 #define CASE(type, size_in_bits) \
259 case sizeof(type): { \
260 type res = __builtin_bswap##size_in_bits(*reinterpret_cast<type*>(&val)); \
261 return *reinterpret_cast<T*>(&res); \
262 }
263 switch (size) {
264 case 1:
265 return val;
266 CASE(uint16_t, 16);
267 CASE(uint32_t, 32);
268 CASE(uint64_t, 64);
269 CASE(__uint128_t, 128);
270 default:
271 UNREACHABLE();
272 }
273 #undef CASE
274 return val;
275 }
276
277 // Read and write memory.
278 inline uint8_t ReadBU(intptr_t addr);
279 inline int8_t ReadB(intptr_t addr);
280 inline void WriteB(intptr_t addr, uint8_t value);
281 inline void WriteB(intptr_t addr, int8_t value);
282
283 inline uint16_t ReadHU(intptr_t addr);
284 inline int16_t ReadH(intptr_t addr);
285 // Note: Overloaded on the sign of the value.
286 inline void WriteH(intptr_t addr, uint16_t value);
287 inline void WriteH(intptr_t addr, int16_t value);
288
289 inline uint32_t ReadWU(intptr_t addr);
290 inline int32_t ReadW(intptr_t addr);
291 inline int64_t ReadW64(intptr_t addr);
292 inline void WriteW(intptr_t addr, uint32_t value);
293 inline void WriteW(intptr_t addr, int32_t value);
294
295 inline int64_t ReadDW(intptr_t addr);
296 inline double ReadDouble(intptr_t addr);
297 inline float ReadFloat(intptr_t addr);
298 inline void WriteDW(intptr_t addr, int64_t value);
299
300 // S390
301 void Trace(Instruction* instr);
302
303 template <typename T>
SetS390ConditionCode(T lhs,T rhs)304 void SetS390ConditionCode(T lhs, T rhs) {
305 condition_reg_ = 0;
306 if (lhs == rhs) {
307 condition_reg_ |= CC_EQ;
308 } else if (lhs < rhs) {
309 condition_reg_ |= CC_LT;
310 } else if (lhs > rhs) {
311 condition_reg_ |= CC_GT;
312 }
313
314 // We get down here only for floating point
315 // comparisons and the values are unordered
316 // i.e. NaN
317 if (condition_reg_ == 0) condition_reg_ = unordered;
318 }
319
320 // Used by arithmetic operations that use carry.
321 template <typename T>
SetS390ConditionCodeCarry(T result,bool overflow)322 void SetS390ConditionCodeCarry(T result, bool overflow) {
323 condition_reg_ = 0;
324 bool zero_result = (result == static_cast<T>(0));
325 if (zero_result && !overflow) {
326 condition_reg_ |= 8;
327 } else if (!zero_result && !overflow) {
328 condition_reg_ |= 4;
329 } else if (zero_result && overflow) {
330 condition_reg_ |= 2;
331 } else if (!zero_result && overflow) {
332 condition_reg_ |= 1;
333 }
334 if (condition_reg_ == 0) UNREACHABLE();
335 }
336
isNaN(double value)337 bool isNaN(double value) { return (value != value); }
338
339 // Set the condition code for bitwise operations
340 // CC0 is set if value == 0.
341 // CC1 is set if value != 0.
342 // CC2/CC3 are not set.
343 template <typename T>
SetS390BitWiseConditionCode(T value)344 void SetS390BitWiseConditionCode(T value) {
345 condition_reg_ = 0;
346
347 if (value == 0)
348 condition_reg_ |= CC_EQ;
349 else
350 condition_reg_ |= CC_LT;
351 }
352
SetS390OverflowCode(bool isOF)353 void SetS390OverflowCode(bool isOF) {
354 if (isOF) condition_reg_ = CC_OF;
355 }
356
TestConditionCode(Condition mask)357 bool TestConditionCode(Condition mask) {
358 // Check for unconditional branch
359 if (mask == 0xf) return true;
360
361 return (condition_reg_ & mask) != 0;
362 }
363
364 // Executes one instruction.
365 void ExecuteInstruction(Instruction* instr, bool auto_incr_pc = true);
366
367 // ICache.
368 static void CheckICache(base::CustomMatcherHashMap* i_cache,
369 Instruction* instr);
370 static void FlushOnePage(base::CustomMatcherHashMap* i_cache, intptr_t start,
371 int size);
372 static CachePage* GetCachePage(base::CustomMatcherHashMap* i_cache,
373 void* page);
374
375 // Handle arguments and return value for runtime FP functions.
376 void GetFpArgs(double* x, double* y, intptr_t* z);
377 void SetFpResult(const double& result);
378 void TrashCallerSaveRegisters();
379
380 void CallInternal(Address entry, int reg_arg_count = 3);
381
382 // Architecture state.
383 // On z9 and higher and supported Linux on z Systems platforms, all registers
384 // are 64-bit, even in 31-bit mode.
385 uint64_t registers_[kNumGPRs];
386 union fpr_t {
387 int8_t int8[16];
388 uint8_t uint8[16];
389 int16_t int16[8];
390 uint16_t uint16[8];
391 int32_t int32[4];
392 uint32_t uint32[4];
393 int64_t int64[2];
394 uint64_t uint64[2];
395 float f32[4];
396 double f64[2];
397 };
398 fpr_t fp_registers_[kNumFPRs];
399
400 static constexpr fpr_t fp_zero = {{0}};
401
get_simd_register(int reg)402 fpr_t get_simd_register(int reg) { return fp_registers_[reg]; }
403
set_simd_register(int reg,const fpr_t & value)404 void set_simd_register(int reg, const fpr_t& value) {
405 fp_registers_[reg] = value;
406 }
407
408 // Vector register lane numbers on IBM machines are reversed compared to
409 // x64. For example, doing an I32x4 extract_lane with lane number 0 on x64
410 // will be equal to lane number 3 on IBM machines. Vector registers are only
411 // used for compiling Wasm code at the moment. Wasm is also little endian
412 // enforced. On s390 native, we manually do a reverse byte whenever values are
413 // loaded/stored from memory to a Simd register. On the simulator however, we
414 // do not reverse the bytes and data is just copied as is from one memory
415 // location to another location which represents a register. To keep the Wasm
416 // simulation accurate, we need to make sure accessing a lane is correctly
417 // simulated and as such we reverse the lane number on the getters and setters
418 // below. We need to be careful when getting/setting values on the Low or High
419 // side of a simulated register. In the simulation, "Low" is equal to the MSB
420 // and "High" is equal to the LSB on memory. "force_ibm_lane_numbering" could
421 // be used to disabled automatic lane number reversal and help with accessing
422 // the Low or High side of a simulated register.
423 template <class T>
424 T get_simd_register_by_lane(int reg, int lane,
425 bool force_ibm_lane_numbering = true) {
426 if (force_ibm_lane_numbering) {
427 lane = (kSimd128Size / sizeof(T)) - 1 - lane;
428 }
429 CHECK_LE(lane, kSimd128Size / sizeof(T));
430 CHECK_LT(reg, kNumFPRs);
431 CHECK_GE(lane, 0);
432 CHECK_GE(reg, 0);
433 return (reinterpret_cast<T*>(&fp_registers_[reg]))[lane];
434 }
435
436 template <class T>
437 void set_simd_register_by_lane(int reg, int lane, const T& value,
438 bool force_ibm_lane_numbering = true) {
439 if (force_ibm_lane_numbering) {
440 lane = (kSimd128Size / sizeof(T)) - 1 - lane;
441 }
442 CHECK_LE(lane, kSimd128Size / sizeof(T));
443 CHECK_LT(reg, kNumFPRs);
444 CHECK_GE(lane, 0);
445 CHECK_GE(reg, 0);
446 (reinterpret_cast<T*>(&fp_registers_[reg]))[lane] = value;
447 }
448
449 // Condition Code register. In S390, the last 4 bits are used.
450 int32_t condition_reg_;
451 // Special register to track PC.
452 intptr_t special_reg_pc_;
453
454 // Simulator support.
455 char* stack_;
456 static const size_t stack_protection_size_ = 256 * kSystemPointerSize;
457 bool pc_modified_;
458 int64_t icount_;
459
460 // Debugger input.
461 char* last_debugger_input_;
462
463 // Registered breakpoints.
464 Instruction* break_pc_;
465 Instr break_instr_;
466
467 v8::internal::Isolate* isolate_;
468
469 // A stop is watched if its code is less than kNumOfWatchedStops.
470 // Only watched stops support enabling/disabling and the counter feature.
471 static const uint32_t kNumOfWatchedStops = 256;
472
473 // Breakpoint is disabled if bit 31 is set.
474 static const uint32_t kStopDisabledBit = 1 << 31;
475
476 // A stop is enabled, meaning the simulator will stop when meeting the
477 // instruction, if bit 31 of watched_stops_[code].count is unset.
478 // The value watched_stops_[code].count & ~(1 << 31) indicates how many times
479 // the breakpoint was hit or gone through.
480 struct StopCountAndDesc {
481 uint32_t count;
482 char* desc;
483 };
484 StopCountAndDesc watched_stops_[kNumOfWatchedStops];
485 void DebugStart();
486
487 int DecodeInstructionOriginal(Instruction* instr);
488 int DecodeInstruction(Instruction* instr);
489 int Evaluate_Unknown(Instruction* instr);
490 #define MAX_NUM_OPCODES (1 << 16)
491 using EvaluateFuncType = int (Simulator::*)(Instruction*);
492
493 static EvaluateFuncType EvalTable[MAX_NUM_OPCODES];
494 static void EvalTableInit();
495
496 #define EVALUATE(name) int Evaluate_##name(Instruction* instr)
497 #define EVALUATE_VR_INSTRUCTIONS(name, op_name, op_value) EVALUATE(op_name);
498 S390_VRR_A_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
499 S390_VRR_C_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
500 S390_VRR_E_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
501 S390_VRR_F_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
502 S390_VRX_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
503 S390_VRS_A_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
504 S390_VRS_B_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
505 S390_VRS_C_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
506 S390_VRR_B_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
507 S390_VRI_A_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
508 S390_VRI_C_OPCODE_LIST(EVALUATE_VR_INSTRUCTIONS)
509 #undef EVALUATE_VR_INSTRUCTIONS
510
511 EVALUATE(DUMY);
512 EVALUATE(BKPT);
513 EVALUATE(SPM);
514 EVALUATE(BALR);
515 EVALUATE(BCTR);
516 EVALUATE(BCR);
517 EVALUATE(SVC);
518 EVALUATE(BSM);
519 EVALUATE(BASSM);
520 EVALUATE(BASR);
521 EVALUATE(MVCL);
522 EVALUATE(CLCL);
523 EVALUATE(LPR);
524 EVALUATE(LNR);
525 EVALUATE(LTR);
526 EVALUATE(LCR);
527 EVALUATE(NR);
528 EVALUATE(CLR);
529 EVALUATE(OR);
530 EVALUATE(XR);
531 EVALUATE(LR);
532 EVALUATE(CR);
533 EVALUATE(AR);
534 EVALUATE(SR);
535 EVALUATE(MR);
536 EVALUATE(DR);
537 EVALUATE(ALR);
538 EVALUATE(SLR);
539 EVALUATE(LDR);
540 EVALUATE(CDR);
541 EVALUATE(LER);
542 EVALUATE(STH);
543 EVALUATE(LA);
544 EVALUATE(STC);
545 EVALUATE(IC_z);
546 EVALUATE(EX);
547 EVALUATE(BAL);
548 EVALUATE(BCT);
549 EVALUATE(BC);
550 EVALUATE(LH);
551 EVALUATE(CH);
552 EVALUATE(AH);
553 EVALUATE(SH);
554 EVALUATE(MH);
555 EVALUATE(BAS);
556 EVALUATE(CVD);
557 EVALUATE(CVB);
558 EVALUATE(ST);
559 EVALUATE(LAE);
560 EVALUATE(N);
561 EVALUATE(CL);
562 EVALUATE(O);
563 EVALUATE(X);
564 EVALUATE(L);
565 EVALUATE(C);
566 EVALUATE(A);
567 EVALUATE(S);
568 EVALUATE(M);
569 EVALUATE(D);
570 EVALUATE(AL);
571 EVALUATE(SL);
572 EVALUATE(STD);
573 EVALUATE(LD);
574 EVALUATE(CD);
575 EVALUATE(STE);
576 EVALUATE(MS);
577 EVALUATE(LE);
578 EVALUATE(BRXH);
579 EVALUATE(BRXLE);
580 EVALUATE(BXH);
581 EVALUATE(BXLE);
582 EVALUATE(SRL);
583 EVALUATE(SLL);
584 EVALUATE(SRA);
585 EVALUATE(SLA);
586 EVALUATE(SRDL);
587 EVALUATE(SLDL);
588 EVALUATE(SRDA);
589 EVALUATE(SLDA);
590 EVALUATE(STM);
591 EVALUATE(TM);
592 EVALUATE(MVI);
593 EVALUATE(TS);
594 EVALUATE(NI);
595 EVALUATE(CLI);
596 EVALUATE(OI);
597 EVALUATE(XI);
598 EVALUATE(LM);
599 EVALUATE(CS);
600 EVALUATE(MVCLE);
601 EVALUATE(CLCLE);
602 EVALUATE(MC);
603 EVALUATE(CDS);
604 EVALUATE(STCM);
605 EVALUATE(ICM);
606 EVALUATE(BPRP);
607 EVALUATE(BPP);
608 EVALUATE(TRTR);
609 EVALUATE(MVN);
610 EVALUATE(MVC);
611 EVALUATE(MVZ);
612 EVALUATE(NC);
613 EVALUATE(CLC);
614 EVALUATE(OC);
615 EVALUATE(XC);
616 EVALUATE(MVCP);
617 EVALUATE(TR);
618 EVALUATE(TRT);
619 EVALUATE(ED);
620 EVALUATE(EDMK);
621 EVALUATE(PKU);
622 EVALUATE(UNPKU);
623 EVALUATE(MVCIN);
624 EVALUATE(PKA);
625 EVALUATE(UNPKA);
626 EVALUATE(PLO);
627 EVALUATE(LMD);
628 EVALUATE(SRP);
629 EVALUATE(MVO);
630 EVALUATE(PACK);
631 EVALUATE(UNPK);
632 EVALUATE(ZAP);
633 EVALUATE(AP);
634 EVALUATE(SP);
635 EVALUATE(MP);
636 EVALUATE(DP);
637 EVALUATE(UPT);
638 EVALUATE(PFPO);
639 EVALUATE(IIHH);
640 EVALUATE(IIHL);
641 EVALUATE(IILH);
642 EVALUATE(IILL);
643 EVALUATE(NIHH);
644 EVALUATE(NIHL);
645 EVALUATE(NILH);
646 EVALUATE(NILL);
647 EVALUATE(OIHH);
648 EVALUATE(OIHL);
649 EVALUATE(OILH);
650 EVALUATE(OILL);
651 EVALUATE(LLIHH);
652 EVALUATE(LLIHL);
653 EVALUATE(LLILH);
654 EVALUATE(LLILL);
655 EVALUATE(TMLH);
656 EVALUATE(TMLL);
657 EVALUATE(TMHH);
658 EVALUATE(TMHL);
659 EVALUATE(BRC);
660 EVALUATE(BRAS);
661 EVALUATE(BRCT);
662 EVALUATE(BRCTG);
663 EVALUATE(LHI);
664 EVALUATE(LGHI);
665 EVALUATE(AHI);
666 EVALUATE(AGHI);
667 EVALUATE(MHI);
668 EVALUATE(MGHI);
669 EVALUATE(CHI);
670 EVALUATE(CGHI);
671 EVALUATE(LARL);
672 EVALUATE(LGFI);
673 EVALUATE(BRCL);
674 EVALUATE(BRASL);
675 EVALUATE(XIHF);
676 EVALUATE(XILF);
677 EVALUATE(IIHF);
678 EVALUATE(IILF);
679 EVALUATE(NIHF);
680 EVALUATE(NILF);
681 EVALUATE(OIHF);
682 EVALUATE(OILF);
683 EVALUATE(LLIHF);
684 EVALUATE(LLILF);
685 EVALUATE(MSGFI);
686 EVALUATE(MSFI);
687 EVALUATE(SLGFI);
688 EVALUATE(SLFI);
689 EVALUATE(AGFI);
690 EVALUATE(AFI);
691 EVALUATE(ALGFI);
692 EVALUATE(ALFI);
693 EVALUATE(CGFI);
694 EVALUATE(CFI);
695 EVALUATE(CLGFI);
696 EVALUATE(CLFI);
697 EVALUATE(LLHRL);
698 EVALUATE(LGHRL);
699 EVALUATE(LHRL);
700 EVALUATE(LLGHRL);
701 EVALUATE(STHRL);
702 EVALUATE(LGRL);
703 EVALUATE(STGRL);
704 EVALUATE(LGFRL);
705 EVALUATE(LRL);
706 EVALUATE(LLGFRL);
707 EVALUATE(STRL);
708 EVALUATE(EXRL);
709 EVALUATE(PFDRL);
710 EVALUATE(CGHRL);
711 EVALUATE(CHRL);
712 EVALUATE(CGRL);
713 EVALUATE(CGFRL);
714 EVALUATE(ECTG);
715 EVALUATE(CSST);
716 EVALUATE(LPD);
717 EVALUATE(LPDG);
718 EVALUATE(BRCTH);
719 EVALUATE(AIH);
720 EVALUATE(ALSIH);
721 EVALUATE(ALSIHN);
722 EVALUATE(CIH);
723 EVALUATE(CLIH);
724 EVALUATE(STCK);
725 EVALUATE(CFC);
726 EVALUATE(IPM);
727 EVALUATE(HSCH);
728 EVALUATE(MSCH);
729 EVALUATE(SSCH);
730 EVALUATE(STSCH);
731 EVALUATE(TSCH);
732 EVALUATE(TPI);
733 EVALUATE(SAL);
734 EVALUATE(RSCH);
735 EVALUATE(STCRW);
736 EVALUATE(STCPS);
737 EVALUATE(RCHP);
738 EVALUATE(SCHM);
739 EVALUATE(CKSM);
740 EVALUATE(SAR);
741 EVALUATE(EAR);
742 EVALUATE(MSR);
743 EVALUATE(MSRKC);
744 EVALUATE(MVST);
745 EVALUATE(CUSE);
746 EVALUATE(SRST);
747 EVALUATE(XSCH);
748 EVALUATE(STCKE);
749 EVALUATE(STCKF);
750 EVALUATE(SRNM);
751 EVALUATE(STFPC);
752 EVALUATE(LFPC);
753 EVALUATE(TRE);
754 EVALUATE(CUUTF);
755 EVALUATE(CUTFU);
756 EVALUATE(STFLE);
757 EVALUATE(SRNMB);
758 EVALUATE(SRNMT);
759 EVALUATE(LFAS);
760 EVALUATE(PPA);
761 EVALUATE(ETND);
762 EVALUATE(TEND);
763 EVALUATE(NIAI);
764 EVALUATE(TABORT);
765 EVALUATE(TRAP4);
766 EVALUATE(LPEBR);
767 EVALUATE(LNEBR);
768 EVALUATE(LTEBR);
769 EVALUATE(LCEBR);
770 EVALUATE(LDEBR);
771 EVALUATE(LXDBR);
772 EVALUATE(LXEBR);
773 EVALUATE(MXDBR);
774 EVALUATE(KEBR);
775 EVALUATE(CEBR);
776 EVALUATE(AEBR);
777 EVALUATE(SEBR);
778 EVALUATE(MDEBR);
779 EVALUATE(DEBR);
780 EVALUATE(MAEBR);
781 EVALUATE(MSEBR);
782 EVALUATE(LPDBR);
783 EVALUATE(LNDBR);
784 EVALUATE(LTDBR);
785 EVALUATE(LCDBR);
786 EVALUATE(SQEBR);
787 EVALUATE(SQDBR);
788 EVALUATE(SQXBR);
789 EVALUATE(MEEBR);
790 EVALUATE(KDBR);
791 EVALUATE(CDBR);
792 EVALUATE(ADBR);
793 EVALUATE(SDBR);
794 EVALUATE(MDBR);
795 EVALUATE(DDBR);
796 EVALUATE(MADBR);
797 EVALUATE(MSDBR);
798 EVALUATE(LPXBR);
799 EVALUATE(LNXBR);
800 EVALUATE(LTXBR);
801 EVALUATE(LCXBR);
802 EVALUATE(LEDBRA);
803 EVALUATE(LDXBRA);
804 EVALUATE(LEXBRA);
805 EVALUATE(FIXBRA);
806 EVALUATE(KXBR);
807 EVALUATE(CXBR);
808 EVALUATE(AXBR);
809 EVALUATE(SXBR);
810 EVALUATE(MXBR);
811 EVALUATE(DXBR);
812 EVALUATE(TBEDR);
813 EVALUATE(TBDR);
814 EVALUATE(DIEBR);
815 EVALUATE(FIEBRA);
816 EVALUATE(THDER);
817 EVALUATE(THDR);
818 EVALUATE(DIDBR);
819 EVALUATE(FIDBRA);
820 EVALUATE(LXR);
821 EVALUATE(LPDFR);
822 EVALUATE(LNDFR);
823 EVALUATE(LCDFR);
824 EVALUATE(LZER);
825 EVALUATE(LZDR);
826 EVALUATE(LZXR);
827 EVALUATE(SFPC);
828 EVALUATE(SFASR);
829 EVALUATE(EFPC);
830 EVALUATE(CELFBR);
831 EVALUATE(CDLFBR);
832 EVALUATE(CXLFBR);
833 EVALUATE(CEFBRA);
834 EVALUATE(CDFBRA);
835 EVALUATE(CXFBRA);
836 EVALUATE(CFEBRA);
837 EVALUATE(CFDBRA);
838 EVALUATE(CFXBRA);
839 EVALUATE(CLFEBR);
840 EVALUATE(CLFDBR);
841 EVALUATE(CLFXBR);
842 EVALUATE(CELGBR);
843 EVALUATE(CDLGBR);
844 EVALUATE(CXLGBR);
845 EVALUATE(CEGBRA);
846 EVALUATE(CDGBRA);
847 EVALUATE(CXGBRA);
848 EVALUATE(CGEBRA);
849 EVALUATE(CGDBRA);
850 EVALUATE(CGXBRA);
851 EVALUATE(CLGEBR);
852 EVALUATE(CLGDBR);
853 EVALUATE(CFER);
854 EVALUATE(CFDR);
855 EVALUATE(CFXR);
856 EVALUATE(LDGR);
857 EVALUATE(CGER);
858 EVALUATE(CGDR);
859 EVALUATE(CGXR);
860 EVALUATE(LGDR);
861 EVALUATE(MDTR);
862 EVALUATE(MDTRA);
863 EVALUATE(DDTRA);
864 EVALUATE(ADTRA);
865 EVALUATE(SDTRA);
866 EVALUATE(LDETR);
867 EVALUATE(LEDTR);
868 EVALUATE(LTDTR);
869 EVALUATE(FIDTR);
870 EVALUATE(MXTRA);
871 EVALUATE(DXTRA);
872 EVALUATE(AXTRA);
873 EVALUATE(SXTRA);
874 EVALUATE(LXDTR);
875 EVALUATE(LDXTR);
876 EVALUATE(LTXTR);
877 EVALUATE(FIXTR);
878 EVALUATE(KDTR);
879 EVALUATE(CGDTRA);
880 EVALUATE(CUDTR);
881 EVALUATE(CDTR);
882 EVALUATE(EEDTR);
883 EVALUATE(ESDTR);
884 EVALUATE(KXTR);
885 EVALUATE(CGXTRA);
886 EVALUATE(CUXTR);
887 EVALUATE(CSXTR);
888 EVALUATE(CXTR);
889 EVALUATE(EEXTR);
890 EVALUATE(ESXTR);
891 EVALUATE(CDGTRA);
892 EVALUATE(CDUTR);
893 EVALUATE(CDSTR);
894 EVALUATE(CEDTR);
895 EVALUATE(QADTR);
896 EVALUATE(IEDTR);
897 EVALUATE(RRDTR);
898 EVALUATE(CXGTRA);
899 EVALUATE(CXUTR);
900 EVALUATE(CXSTR);
901 EVALUATE(CEXTR);
902 EVALUATE(QAXTR);
903 EVALUATE(IEXTR);
904 EVALUATE(RRXTR);
905 EVALUATE(LPGR);
906 EVALUATE(LNGR);
907 EVALUATE(LTGR);
908 EVALUATE(LCGR);
909 EVALUATE(LGR);
910 EVALUATE(LGBR);
911 EVALUATE(LGHR);
912 EVALUATE(AGR);
913 EVALUATE(SGR);
914 EVALUATE(ALGR);
915 EVALUATE(SLGR);
916 EVALUATE(MSGR);
917 EVALUATE(MSGRKC);
918 EVALUATE(DSGR);
919 EVALUATE(LRVGR);
920 EVALUATE(LPGFR);
921 EVALUATE(LNGFR);
922 EVALUATE(LTGFR);
923 EVALUATE(LCGFR);
924 EVALUATE(LGFR);
925 EVALUATE(LLGFR);
926 EVALUATE(LLGTR);
927 EVALUATE(AGFR);
928 EVALUATE(SGFR);
929 EVALUATE(ALGFR);
930 EVALUATE(SLGFR);
931 EVALUATE(MSGFR);
932 EVALUATE(DSGFR);
933 EVALUATE(KMAC);
934 EVALUATE(LRVR);
935 EVALUATE(CGR);
936 EVALUATE(CLGR);
937 EVALUATE(LBR);
938 EVALUATE(LHR);
939 EVALUATE(KMF);
940 EVALUATE(KMO);
941 EVALUATE(PCC);
942 EVALUATE(KMCTR);
943 EVALUATE(KM);
944 EVALUATE(KMC);
945 EVALUATE(CGFR);
946 EVALUATE(KIMD);
947 EVALUATE(KLMD);
948 EVALUATE(CFDTR);
949 EVALUATE(CLGDTR);
950 EVALUATE(CLFDTR);
951 EVALUATE(BCTGR);
952 EVALUATE(CFXTR);
953 EVALUATE(CLFXTR);
954 EVALUATE(CDFTR);
955 EVALUATE(CDLGTR);
956 EVALUATE(CDLFTR);
957 EVALUATE(CXFTR);
958 EVALUATE(CXLGTR);
959 EVALUATE(CXLFTR);
960 EVALUATE(CGRT);
961 EVALUATE(NGR);
962 EVALUATE(OGR);
963 EVALUATE(XGR);
964 EVALUATE(FLOGR);
965 EVALUATE(LLGCR);
966 EVALUATE(LLGHR);
967 EVALUATE(MLGR);
968 EVALUATE(DLGR);
969 EVALUATE(ALCGR);
970 EVALUATE(SLBGR);
971 EVALUATE(EPSW);
972 EVALUATE(TRTT);
973 EVALUATE(TRTO);
974 EVALUATE(TROT);
975 EVALUATE(TROO);
976 EVALUATE(LLCR);
977 EVALUATE(LLHR);
978 EVALUATE(MLR);
979 EVALUATE(DLR);
980 EVALUATE(ALCR);
981 EVALUATE(SLBR);
982 EVALUATE(CU14);
983 EVALUATE(CU24);
984 EVALUATE(CU41);
985 EVALUATE(CU42);
986 EVALUATE(TRTRE);
987 EVALUATE(SRSTU);
988 EVALUATE(TRTE);
989 EVALUATE(AHHHR);
990 EVALUATE(SHHHR);
991 EVALUATE(ALHHHR);
992 EVALUATE(SLHHHR);
993 EVALUATE(CHHR);
994 EVALUATE(AHHLR);
995 EVALUATE(SHHLR);
996 EVALUATE(ALHHLR);
997 EVALUATE(SLHHLR);
998 EVALUATE(CHLR);
999 EVALUATE(POPCNT_Z);
1000 EVALUATE(LOCGR);
1001 EVALUATE(NGRK);
1002 EVALUATE(OGRK);
1003 EVALUATE(XGRK);
1004 EVALUATE(AGRK);
1005 EVALUATE(SGRK);
1006 EVALUATE(ALGRK);
1007 EVALUATE(SLGRK);
1008 EVALUATE(LOCR);
1009 EVALUATE(NRK);
1010 EVALUATE(ORK);
1011 EVALUATE(XRK);
1012 EVALUATE(ARK);
1013 EVALUATE(SRK);
1014 EVALUATE(ALRK);
1015 EVALUATE(SLRK);
1016 EVALUATE(LTG);
1017 EVALUATE(LG);
1018 EVALUATE(CVBY);
1019 EVALUATE(AG);
1020 EVALUATE(SG);
1021 EVALUATE(ALG);
1022 EVALUATE(SLG);
1023 EVALUATE(MSG);
1024 EVALUATE(DSG);
1025 EVALUATE(CVBG);
1026 EVALUATE(LRVG);
1027 EVALUATE(LT);
1028 EVALUATE(LGF);
1029 EVALUATE(LGH);
1030 EVALUATE(LLGF);
1031 EVALUATE(LLGT);
1032 EVALUATE(AGF);
1033 EVALUATE(SGF);
1034 EVALUATE(ALGF);
1035 EVALUATE(SLGF);
1036 EVALUATE(MSGF);
1037 EVALUATE(DSGF);
1038 EVALUATE(LRV);
1039 EVALUATE(LRVH);
1040 EVALUATE(CG);
1041 EVALUATE(CLG);
1042 EVALUATE(STG);
1043 EVALUATE(NTSTG);
1044 EVALUATE(CVDY);
1045 EVALUATE(CVDG);
1046 EVALUATE(STRVG);
1047 EVALUATE(CGF);
1048 EVALUATE(CLGF);
1049 EVALUATE(LTGF);
1050 EVALUATE(CGH);
1051 EVALUATE(PFD);
1052 EVALUATE(STRV);
1053 EVALUATE(STRVH);
1054 EVALUATE(BCTG);
1055 EVALUATE(STY);
1056 EVALUATE(MSY);
1057 EVALUATE(MSC);
1058 EVALUATE(NY);
1059 EVALUATE(CLY);
1060 EVALUATE(OY);
1061 EVALUATE(XY);
1062 EVALUATE(LY);
1063 EVALUATE(CY);
1064 EVALUATE(AY);
1065 EVALUATE(SY);
1066 EVALUATE(MFY);
1067 EVALUATE(ALY);
1068 EVALUATE(SLY);
1069 EVALUATE(STHY);
1070 EVALUATE(LAY);
1071 EVALUATE(STCY);
1072 EVALUATE(ICY);
1073 EVALUATE(LAEY);
1074 EVALUATE(LB);
1075 EVALUATE(LGB);
1076 EVALUATE(LHY);
1077 EVALUATE(CHY);
1078 EVALUATE(AHY);
1079 EVALUATE(SHY);
1080 EVALUATE(MHY);
1081 EVALUATE(NG);
1082 EVALUATE(OG);
1083 EVALUATE(XG);
1084 EVALUATE(LGAT);
1085 EVALUATE(MLG);
1086 EVALUATE(DLG);
1087 EVALUATE(ALCG);
1088 EVALUATE(SLBG);
1089 EVALUATE(STPQ);
1090 EVALUATE(LPQ);
1091 EVALUATE(LLGC);
1092 EVALUATE(LLGH);
1093 EVALUATE(LLC);
1094 EVALUATE(LLH);
1095 EVALUATE(ML);
1096 EVALUATE(DL);
1097 EVALUATE(ALC);
1098 EVALUATE(SLB);
1099 EVALUATE(LLGTAT);
1100 EVALUATE(LLGFAT);
1101 EVALUATE(LAT);
1102 EVALUATE(LBH);
1103 EVALUATE(LLCH);
1104 EVALUATE(STCH);
1105 EVALUATE(LHH);
1106 EVALUATE(LLHH);
1107 EVALUATE(STHH);
1108 EVALUATE(LFHAT);
1109 EVALUATE(LFH);
1110 EVALUATE(STFH);
1111 EVALUATE(CHF);
1112 EVALUATE(MVCDK);
1113 EVALUATE(MVHHI);
1114 EVALUATE(MVGHI);
1115 EVALUATE(MVHI);
1116 EVALUATE(CHHSI);
1117 EVALUATE(CGHSI);
1118 EVALUATE(CHSI);
1119 EVALUATE(CLFHSI);
1120 EVALUATE(TBEGIN);
1121 EVALUATE(TBEGINC);
1122 EVALUATE(LMG);
1123 EVALUATE(SRAG);
1124 EVALUATE(SLAG);
1125 EVALUATE(SRLG);
1126 EVALUATE(SLLG);
1127 EVALUATE(CSY);
1128 EVALUATE(CSG);
1129 EVALUATE(RLLG);
1130 EVALUATE(RLL);
1131 EVALUATE(STMG);
1132 EVALUATE(STMH);
1133 EVALUATE(STCMH);
1134 EVALUATE(STCMY);
1135 EVALUATE(CDSY);
1136 EVALUATE(CDSG);
1137 EVALUATE(BXHG);
1138 EVALUATE(BXLEG);
1139 EVALUATE(ECAG);
1140 EVALUATE(TMY);
1141 EVALUATE(MVIY);
1142 EVALUATE(NIY);
1143 EVALUATE(CLIY);
1144 EVALUATE(OIY);
1145 EVALUATE(XIY);
1146 EVALUATE(ASI);
1147 EVALUATE(ALSI);
1148 EVALUATE(AGSI);
1149 EVALUATE(ALGSI);
1150 EVALUATE(ICMH);
1151 EVALUATE(ICMY);
1152 EVALUATE(MVCLU);
1153 EVALUATE(CLCLU);
1154 EVALUATE(STMY);
1155 EVALUATE(LMH);
1156 EVALUATE(LMY);
1157 EVALUATE(TP);
1158 EVALUATE(SRAK);
1159 EVALUATE(SLAK);
1160 EVALUATE(SRLK);
1161 EVALUATE(SLLK);
1162 EVALUATE(LOCG);
1163 EVALUATE(STOCG);
1164 EVALUATE(LANG);
1165 EVALUATE(LAOG);
1166 EVALUATE(LAXG);
1167 EVALUATE(LAAG);
1168 EVALUATE(LAALG);
1169 EVALUATE(LOC);
1170 EVALUATE(STOC);
1171 EVALUATE(LAN);
1172 EVALUATE(LAO);
1173 EVALUATE(LAX);
1174 EVALUATE(LAA);
1175 EVALUATE(LAAL);
1176 EVALUATE(BRXHG);
1177 EVALUATE(BRXLG);
1178 EVALUATE(RISBLG);
1179 EVALUATE(RNSBG);
1180 EVALUATE(RISBG);
1181 EVALUATE(ROSBG);
1182 EVALUATE(RXSBG);
1183 EVALUATE(RISBGN);
1184 EVALUATE(RISBHG);
1185 EVALUATE(CGRJ);
1186 EVALUATE(CGIT);
1187 EVALUATE(CIT);
1188 EVALUATE(CLFIT);
1189 EVALUATE(CGIJ);
1190 EVALUATE(CIJ);
1191 EVALUATE(AHIK);
1192 EVALUATE(AGHIK);
1193 EVALUATE(ALHSIK);
1194 EVALUATE(ALGHSIK);
1195 EVALUATE(CGRB);
1196 EVALUATE(CGIB);
1197 EVALUATE(CIB);
1198 EVALUATE(LDEB);
1199 EVALUATE(LXDB);
1200 EVALUATE(LXEB);
1201 EVALUATE(MXDB);
1202 EVALUATE(KEB);
1203 EVALUATE(CEB);
1204 EVALUATE(AEB);
1205 EVALUATE(SEB);
1206 EVALUATE(MDEB);
1207 EVALUATE(DEB);
1208 EVALUATE(MAEB);
1209 EVALUATE(MSEB);
1210 EVALUATE(TCEB);
1211 EVALUATE(TCDB);
1212 EVALUATE(TCXB);
1213 EVALUATE(SQEB);
1214 EVALUATE(SQDB);
1215 EVALUATE(MEEB);
1216 EVALUATE(KDB);
1217 EVALUATE(CDB);
1218 EVALUATE(ADB);
1219 EVALUATE(SDB);
1220 EVALUATE(MDB);
1221 EVALUATE(DDB);
1222 EVALUATE(MADB);
1223 EVALUATE(MSDB);
1224 EVALUATE(SLDT);
1225 EVALUATE(SRDT);
1226 EVALUATE(SLXT);
1227 EVALUATE(SRXT);
1228 EVALUATE(TDCET);
1229 EVALUATE(TDGET);
1230 EVALUATE(TDCDT);
1231 EVALUATE(TDGDT);
1232 EVALUATE(TDCXT);
1233 EVALUATE(TDGXT);
1234 EVALUATE(LEY);
1235 EVALUATE(LDY);
1236 EVALUATE(STEY);
1237 EVALUATE(STDY);
1238 EVALUATE(CZDT);
1239 EVALUATE(CZXT);
1240 EVALUATE(CDZT);
1241 EVALUATE(CXZT);
1242 #undef EVALUATE
1243 };
1244
1245 } // namespace internal
1246 } // namespace v8
1247
1248 #endif // defined(USE_SIMULATOR)
1249 #endif // V8_EXECUTION_S390_SIMULATOR_S390_H_
1250