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Searched refs:opnd (Results 1 – 25 of 96) sorted by relevance

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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/
Dreg_alloc_basic.cpp24 Operand *DefaultO0RegAllocator::HandleRegOpnd(Operand &opnd) in HandleRegOpnd() argument
26 DEBUG_ASSERT(opnd.IsRegister(), "Operand should be register operand"); in HandleRegOpnd()
27 auto &regOpnd = static_cast<RegOperand &>(opnd); in HandleRegOpnd()
29 return &opnd; in HandleRegOpnd()
42 (void)allocatedSet.insert(&opnd); in HandleRegOpnd()
46 (void)allocatedSet.insert(&opnd); in HandleRegOpnd()
58 Operand *DefaultO0RegAllocator::HandleMemOpnd(Operand &opnd) in HandleMemOpnd() argument
60 DEBUG_ASSERT(opnd.IsMemoryAccessOperand(), "Operand should be memory access operand"); in HandleMemOpnd()
61 auto *memOpnd = static_cast<MemOperand *>(&opnd); in HandleMemOpnd()
71 (void)allocatedSet.insert(&opnd); in HandleMemOpnd()
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Debo.cpp79 bool Ebo::IsFrameReg(Operand &opnd) const in IsFrameReg()
81 if (!opnd.IsRegister()) { in IsFrameReg()
84 RegOperand &reg = static_cast<RegOperand &>(opnd); in IsFrameReg()
97 bool Ebo::IsSaveReg(const Operand &opnd) in IsSaveReg() argument
99 if (!opnd.IsRegister()) { in IsSaveReg()
102 const RegOperand &reg = static_cast<const RegOperand &>(opnd); in IsSaveReg()
106 bool Ebo::IsPhysicalReg(const Operand &opnd) const in IsPhysicalReg()
108 if (!opnd.IsRegister()) { in IsPhysicalReg()
111 const RegOperand &reg = static_cast<const RegOperand &>(opnd); in IsPhysicalReg()
115 bool Ebo::HasAssignedReg(const Operand &opnd) const in HasAssignedReg()
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Dinsn.cpp200 Operand &opnd = GetOperand(i); in GetMemOpnd() local
201 if (opnd.IsMemoryAccessOperand()) { in GetMemOpnd()
202 return &opnd; in GetMemOpnd()
210 Operand &opnd = GetOperand(i); in SetMemOpnd() local
211 if (opnd.IsMemoryAccessOperand()) { in SetMemOpnd()
228 Operand &opnd = GetOperand(i); in GetDefRegs() local
231 if (!isDef && !opnd.IsMemoryAccessOperand()) { in GetDefRegs()
234 if (opnd.IsList()) { in GetDefRegs()
235 for (auto *op : static_cast<ListOperand &>(opnd).GetOperands()) { in GetDefRegs()
239 } else if (opnd.IsMemoryAccessOperand()) { in GetDefRegs()
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Dpeep.cpp49 Operand &opnd = curInsn->GetOperand(i); in IsCCRegCrossVersion() local
50 if (!opnd.IsRegister()) { in IsCCRegCrossVersion()
53 auto &regOpnd = static_cast<RegOperand &>(opnd); in IsCCRegCrossVersion()
57 if (static_cast<RegOperand &>(opnd).IsOfCC()) { in IsCCRegCrossVersion()
154 Operand &opnd = nextInsn->GetOperand(static_cast<uint32>(i)); in IfOperandIsLiveAfterInsn() local
155 if (opnd.IsMemoryAccessOperand()) { in IfOperandIsLiveAfterInsn()
156 auto &mem = static_cast<MemOperand &>(opnd); in IfOperandIsLiveAfterInsn()
172 } else if (opnd.IsList()) { in IfOperandIsLiveAfterInsn()
173 auto &opndList = static_cast<ListOperand&>(opnd).GetOperands(); in IfOperandIsLiveAfterInsn()
179 if (!opnd.IsRegister()) { in IfOperandIsLiveAfterInsn()
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Dlive.cpp267 Operand &opnd = insn->GetOperand(i); in GetBBDefUse() local
268 if (opnd.IsList()) { in GetBBDefUse()
270 ProcessAsmListOpnd(bb, opnd, i); in GetBBDefUse()
272 ProcessListOpnd(bb, opnd, opndDesc->IsDef()); in GetBBDefUse()
274 } else if (opnd.IsMemoryAccessOperand()) { in GetBBDefUse()
275 ProcessMemOpnd(bb, opnd); in GetBBDefUse()
276 } else if (opnd.IsConditionCode()) { in GetBBDefUse()
281 CollectLiveInfo(bb, opnd, isDef, isUse); in GetBBDefUse()
288 void LiveAnalysis::CollectLiveInfo(BB &bb, const Operand &opnd, bool isDef, bool isUse) const in CollectLiveInfo() argument
290 if (!opnd.IsRegister()) { in CollectLiveInfo()
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Dreg_alloc_lsra.cpp83 bool LSRALinearScanRegAllocator::CheckForReg(Operand &opnd, const Insn &insn, const LiveInterval &l… in CheckForReg() argument
86 if (!opnd.IsRegister()) { in CheckForReg()
89 auto &regOpnd = static_cast<RegOperand &>(opnd); in CheckForReg()
201 Operand &opnd = insn->GetOperand(iSecond); in PrintLiveRangesGraph() local
206 if (opnd.IsList()) { in PrintLiveRangesGraph()
207 auto &listOpnd = static_cast<ListOperand &>(opnd); in PrintLiveRangesGraph()
211 } else if (opnd.IsMemoryAccessOperand()) { in PrintLiveRangesGraph()
212 auto &memOpnd = static_cast<MemOperand &>(opnd); in PrintLiveRangesGraph()
222 (void)CheckForReg(opnd, *insn, *li, regNO, isDef); in PrintLiveRangesGraph()
263 const auto *opnd = item.second; in SpillStackMapInfo() local
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Dcg_pre.cpp181 CgOccur *CGPre::CreateRealOcc(Insn &insn, Operand &opnd, OccType occType) in CreateRealOcc() argument
183 uint64 hashIdx = PreWorkCandHashTable::ComputeWorkCandHashIndex(opnd); in CreateRealOcc()
188 if (currOpnd == &opnd) { in CreateRealOcc()
197 newOcc = ssaPreMemPool->New<CgDefOcc>(insn.GetBB(), &insn, &opnd); in CreateRealOcc()
200 newOcc = ssaPreMemPool->New<CgStoreOcc>(insn.GetBB(), &insn, &opnd); in CreateRealOcc()
203 newOcc = ssaPreMemPool->New<CgUseOcc>(insn.GetBB(), &insn, &opnd); in CreateRealOcc()
216 wkCand = ssaPreMemPool->New<PreWorkCand>(ssaPreAllocator, &opnd, GetPUIdx()); in CreateRealOcc()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
Daarch64_obj_emitter.cpp379 uint32 opnd = GetOpndMachineValue(insn.GetOperand(kInsnFirstOpnd)); in GetBinaryCodeForInsn() local
380 opnd |= GetOpndMachineValue(insn.GetOperand(kInsnSecondOpnd)) << kShiftSixteen; in GetBinaryCodeForInsn()
381 opnd |= (0b11111 << kShiftFive) | AArch64CG::kMd[MOP_wiorrrr].GetMopEncode(); in GetBinaryCodeForInsn()
382 return opnd; in GetBinaryCodeForInsn()
505 uint32 AArch64ObjEmitter::GetOpndMachineValue(const Operand &opnd) const in GetOpndMachineValue()
507 if (opnd.IsRegister()) { in GetOpndMachineValue()
508 const RegOperand &regOpnd = static_cast<const RegOperand &>(opnd); in GetOpndMachineValue()
523 } else if (opnd.IsImmediate()) { in GetOpndMachineValue()
524 return static_cast<uint32>(static_cast<const ImmOperand &>(opnd).GetValue()); in GetOpndMachineValue()
525 } else if (opnd.IsConditionCode()) { in GetOpndMachineValue()
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Daarch64_ra_opt.cpp21 bool RaX0Opt::PropagateX0CanReplace(Operand *opnd, regno_t replaceReg) const in PropagateX0CanReplace() argument
23 if (opnd != nullptr) { in PropagateX0CanReplace()
24 RegOperand *regopnd = static_cast<RegOperand *>(opnd); in PropagateX0CanReplace()
43 Operand &opnd = nInsn->GetOperand(static_cast<uint32>(i)); in PropagateRenameReg() local
45 if (opnd.IsList()) { in PropagateRenameReg()
47 } else if (opnd.IsMemoryAccessOperand()) { in PropagateRenameReg()
48 MemOperand &memopnd = static_cast<MemOperand &>(opnd); in PropagateRenameReg()
57 } else if (opnd.IsRegister()) { in PropagateRenameReg()
59 RegOperand &regopnd = static_cast<RegOperand &>(opnd); in PropagateRenameReg()
99 RegOperand &opnd = static_cast<RegOperand &>(ninsn->GetOperand(index)); in PropagateX0DetectRedefine() local
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Daarch64_reg_coalesce.cpp101 for (auto opnd : static_cast<ListOperand &>(insn.GetOperand(i)).GetOperands()) { in ComputeLiveIntervalsForEachDefOperand()
102 SetupLiveIntervalByOp(*static_cast<RegOperand *>(opnd), insn, true); in ComputeLiveIntervalsForEachDefOperand()
106 Operand &opnd = insn.GetOperand(i); in ComputeLiveIntervalsForEachDefOperand() local
107 if (opnd.IsMemoryAccessOperand()) { in ComputeLiveIntervalsForEachDefOperand()
108 auto &memOpnd = static_cast<MemOperand &>(opnd); in ComputeLiveIntervalsForEachDefOperand()
110 SetupLiveIntervalByOp(opnd, insn, true); in ComputeLiveIntervalsForEachDefOperand()
116 SetupLiveIntervalByOp(opnd, insn, true); in ComputeLiveIntervalsForEachDefOperand()
117 auto *drivedRef = static_cast<RegOperand&>(opnd).GetBaseRefOpnd(); in ComputeLiveIntervalsForEachDefOperand()
130 for (auto opnd : static_cast<ListOperand &>(insn.GetOperand(i)).GetOperands()) { in ComputeLiveIntervalsForEachUseOperand()
131 SetupLiveIntervalByOp(*static_cast<RegOperand *>(opnd), insn, false); in ComputeLiveIntervalsForEachUseOperand()
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Daarch64_offset_adjust.cpp57 Operand &opnd = insn.GetOperand(i); in AdjustmentOffsetForOpnd() local
58 if (opnd.IsRegister()) { in AdjustmentOffsetForOpnd()
59 auto &regOpnd = static_cast<RegOperand&>(opnd); in AdjustmentOffsetForOpnd()
69 } else if (opnd.IsMemoryAccessOperand()) { in AdjustmentOffsetForOpnd()
72 } else if (opnd.IsIntImmediate()) { in AdjustmentOffsetForOpnd()
81 Operand &opnd = insn.GetOperand(i); in AdjustmentOffsetForOpnd() local
82 if (opnd.IsMemoryAccessOperand()) { in AdjustmentOffsetForOpnd()
83 auto &memOpnd = static_cast<MemOperand &>(opnd); in AdjustmentOffsetForOpnd()
96 Operand &opnd = insn.GetOperand(i); in AdjustmentOffsetForOpnd() local
97 if (opnd.IsIntImmediate()) { in AdjustmentOffsetForOpnd()
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Daarch64_reaching.cpp407 Operand &opnd = insn->GetOperand(i); in FindMemDefBetweenInsn() local
409 if (opnd.IsMemoryAccessOperand()) { in FindMemDefBetweenInsn()
410 auto &memOpnd = static_cast<MemOperand &>(opnd); in FindMemDefBetweenInsn()
465 Operand &opnd = insn->GetOperand(i); in FindMemDefInBB() local
466 if (opnd.IsMemoryAccessOperand()) { in FindMemDefInBB()
467 auto &memOpnd = static_cast<MemOperand &>(opnd); in FindMemDefInBB()
586 Operand &opnd = insn.GetOperand(indexOrRegNO); in FindDefForRegOpnd() local
587 auto &regOpnd = static_cast<RegOperand &>(opnd); in FindDefForRegOpnd()
794 Operand &opnd = insn->GetOperand(i); in FindRegUsingBetweenInsn() local
795 if (opnd.IsList()) { in FindRegUsingBetweenInsn()
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Daarch64_ssa.cpp28 Operand &opnd = insn.GetOperand(static_cast<uint32>(i)); in RenameInsn() local
31 opnd.Accept(renameVisitor); in RenameInsn()
95 Operand &opnd = curInsn.GetOperand(i); in ReplaceInsn() local
103 opnd.Accept(ssaUpdator); in ReplaceInsn()
135 Operand &opnd = useInsn->GetOperand(opndIt.first); in ReplaceAllUse() local
138 opnd.Accept(replaceRegOpndVisitor); in ReplaceAllUse()
151 Operand &opnd = newInsn.GetOperand(i); in CreateNewInsnSSAInfo() local
157 CHECK_FATAL(opnd.IsRegister(), "defOpnd must be reg"); in CreateNewInsnSSAInfo()
158 auto &defRegOpnd = static_cast<RegOperand &>(opnd); in CreateNewInsnSSAInfo()
173 opnd.Accept(ssaUpdator); in CreateNewInsnSSAInfo()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
Dreg_alloc_basic.h49 bool AllocatePhysicalRegister(const RegOperand &opnd);
53 void AllocHandleDestList(Insn &insn, Operand &opnd, uint32 idx);
54 void AllocHandleDest(Insn &insn, Operand &opnd, uint32 idx);
55 void AllocHandleSrcList(Insn &insn, Operand &opnd, uint32 idx);
56 void AllocHandleSrc(Insn &insn, Operand &opnd, uint32 idx);
58 void SaveCalleeSavedReg(const RegOperand &opnd);
61 Operand *HandleRegOpnd(Operand &opnd);
62 Operand *HandleMemOpnd(Operand &opnd);
63 Operand *AllocSrcOpnd(Operand &opnd);
64 Operand *AllocDestOpnd(Operand &opnd, const Insn &insn);
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Debo.h42 explicit OpndInfo(Operand &opnd) : opnd(&opnd) {} in OpndInfo()
47 Operand *opnd; /* Operand */ member
67 explicit MemOpndInfo(Operand &opnd) : OpndInfo(opnd) {} in MemOpndInfo()
158 bool IsSaveReg(const Operand &opnd);
159 bool IsFrameReg(Operand &opnd) const;
162 bool IsPhysicalReg(const Operand &opnd) const;
163 bool HasAssignedReg(const Operand &opnd) const;
166 …bool ForwardPropCheck(const Operand *opndReplace, const OpndInfo &opndInfo, const Operand &opnd, I…
167 …bool RegForwardCheck(Insn &insn, const Operand &opnd, const Operand *opndReplace, Operand &oldOpnd,
179 void UpdateOpndInfo(const Operand &opnd, OpndInfo &opndInfo, OpndInfo *newInfo, int32 hashVal);
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Dcg_occur.h36 …CgOccur(OccType ty, BB *bb, Insn *insn, Operand *opnd) : occTy(ty), cgBB(bb), insn(insn), opnd(opn… in CgOccur() argument
99 return opnd; in GetOperand()
104 return opnd; in GetOperand()
139 Operand *opnd = nullptr; variable
146 …CgUseOcc(BB *bb, Insn *insn, Operand *opnd) : CgOccur(kOccUse, bb, insn, opnd), needReload(false) … in CgUseOcc() argument
183 CgStoreOcc(BB *bb, Insn *insn, Operand *opnd) : CgOccur(kOccStore, bb, insn, opnd) {} in CgStoreOcc() argument
219 CgDefOcc(BB *bb, Insn *insn, Operand *opnd) : CgOccur(kOccDef, bb, insn, opnd) {} in CgDefOcc() argument
257 CgPhiOcc(BB &bb, Operand *opnd, MapleAllocator &alloc) in CgPhiOcc() argument
258 …: CgOccur(kOccPhiocc, 0, bb, nullptr), regOpnd(opnd), isDownSafe(!bb.IsCatch()), phiOpnds(alloc.Ad… in CgPhiOcc()
301 void AddPhiOpnd(CgPhiOpndOcc &opnd) in AddPhiOpnd() argument
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Doperand.h876 bool operator==(const OfstOperand &opnd) const
878 … return (offsetType == opnd.offsetType && symbol == opnd.symbol && ImmOperand::operator==(opnd) &&
879 relocs == opnd.relocs);
882 bool operator<(const OfstOperand &opnd) const
884 … return (offsetType < opnd.offsetType || (offsetType == opnd.offsetType && symbol < opnd.symbol) ||
885 … (offsetType == opnd.offsetType && symbol == opnd.symbol && GetValue() < opnd.GetValue()));
1291 bool operator<(const MemOperand &opnd) const
1293 if (addrMode != opnd.addrMode) {
1294 return addrMode < opnd.addrMode;
1296 if (GetBaseRegister() != opnd.GetBaseRegister()) {
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Dcfi.h134 Operand *opnd = memPool.Clone<RegOperand>(*this); in Clone() local
135 return opnd; in Clone()
159 Operand *opnd = memPool.Clone<ImmOperand>(*this); in Clone() local
160 return opnd; in Clone()
189 Operand *opnd = memPool.Clone<SymbolOperand>(*this); in Clone() local
190 return opnd; in Clone()
217 Operand *opnd = memPool.Clone<StrOperand>(*this); in Clone() local
218 return opnd; in Clone()
250 Operand *opnd = memPool.Clone<LabelOperand>(*this); in Clone() local
251 return opnd; in Clone()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_me/src/
Dcast_opt.cpp66 PrimType dstType, BaseNode *opnd, TyIdx dstTyIdx) in CreateMapleExprByCastKind() argument
69 …urn mirBuilder.CreateExprExtractbits(OP_zext, dstType, 0, GetPrimTypeActualBitSize(srcType), opnd); in CreateMapleExprByCastKind()
71 …urn mirBuilder.CreateExprExtractbits(OP_sext, dstType, 0, GetPrimTypeActualBitSize(srcType), opnd); in CreateMapleExprByCastKind()
72 } else if (castKind == CAST_retype && srcType == opnd->GetPrimType()) { in CreateMapleExprByCastKind()
77 return mirBuilder.CreateExprRetype(*dstMIRType, srcType, opnd); in CreateMapleExprByCastKind()
79 return mirBuilder.CreateExprTypeCvt(OP_cvt, dstType, srcType, *opnd); in CreateMapleExprByCastKind()
370 auto *opnd = expr->Opnd(0); in SimplifyCast() local
379 Opcode opndOp = opnd->GetOpCode(); in SimplifyCast()
387 BaseNodeCastInfo firstCastInfo(opnd); in SimplifyCast()
416 auto *opnd = castExpr->Opnd(0); in SimplifyCastSingle() local
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Dmeexpr_use_info.cpp85 auto opnd = expr->GetOpnd(opndId); in CollectUseInfoInExpr() local
86 CollectUseInfoInExpr(opnd, stmt); in CollectUseInfoInExpr()
93 auto *opnd = stmt->GetOpnd(opndId); in CollectUseInfoInStmt() local
94 CollectUseInfoInExpr(opnd, stmt); in CollectUseInfoInStmt()
118 auto *opnd = phi->GetOpnd(id); in CollectUseInfoInBB() local
119 AddUseSiteOfExpr(opnd, phi); in CollectUseInfoInBB()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/
Dx64_reaching.cpp49 Operand &opnd = insn->GetOperand(i); in FindRegUseBetweenInsn() local
52 if (regProp->IsDef() && opnd.IsRegister() && in FindRegUseBetweenInsn()
53 (static_cast<RegOperand &>(opnd).GetRegisterNumber() == regNO)) { in FindRegUseBetweenInsn()
57 if (opnd.IsList()) { in FindRegUseBetweenInsn()
58 auto &listOpnd = static_cast<ListOperand &>(opnd); in FindRegUseBetweenInsn()
68 if (!regProp->IsUse() && !opnd.IsMemoryAccessOperand()) { in FindRegUseBetweenInsn()
73 if (opnd.IsMemoryAccessOperand()) { in FindRegUseBetweenInsn()
74 auto &memOpnd = static_cast<MemOperand &>(opnd); in FindRegUseBetweenInsn()
81 } else if (opnd.IsConditionCode()) { in FindRegUseBetweenInsn()
87 … } else if (opnd.IsRegister() && (static_cast<RegOperand &>(opnd).GetRegisterNumber() == regNO)) { in FindRegUseBetweenInsn()
Dx64_local_opt.cpp86 Operand &opnd = insn.GetOperand(i); in propagateOperand() local
87 if (opnd.IsList()) { in propagateOperand()
95 if (regProp->IsUse() && !regProp->IsDef() && opnd.IsRegister()) { in propagateOperand()
96 RegOperand &regOpnd = static_cast<RegOperand &>(opnd); in propagateOperand()
112 Operand &opnd = insn.GetOperand(i); in Optimize() local
115 regDef = static_cast<RegOperand *>(&opnd); in Optimize()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
Daarch64_ebo.h42 const RegOperand &GetRegOperand(const Operand &opnd) const override;
46 bool DoConstProp(Insn &insn, uint32 i, Operand &opnd) override;
60 bool ChangeLdrMop(Insn &insn, const Operand &opnd) const override;
67 bool LiveOutOfBB(const Operand &opnd, const BB &bb) const override;
68 bool IsInvalidReg(const RegOperand &opnd) const override;
69 bool IsZeroRegister(const Operand &opnd) const override;
70 bool IsConstantImmOrReg(const Operand &opnd) const override;
73 const RegOperand &opnd);
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_me/include/
Dssa_mir_nodes.h26 MayDefNode(VersionSt *sym, StmtNode *st) : opnd(sym), result(sym), stmt(st) {} in MayDefNode()
32 return opnd; in GetOpnd()
36 return opnd; in GetOpnd()
64 opnd = sym; in SetOpnd()
76 opnd->Dump(); in Dump()
82 return opnd == other.opnd && result == other.result && stmt == other.stmt;
87 VersionSt *opnd;
94 explicit MayUseNode(VersionSt *sym) : opnd(sym) {} in MayUseNode()
100 return opnd; in GetOpnd()
105 opnd = sym; in SetOpnd()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
Dx64_emitter.h34 assembler::Reg TransferReg(Operand *opnd) const;
35 std::pair<int64, bool> TransferImm(Operand *opnd);
36 assembler::Mem TransferMem(Operand *opnd, uint32 funcUniqueId);
37 int64 TransferLabel(Operand *opnd, uint32 funcUniqueId);
38 uint32 TransferFuncName(Operand *opnd);

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