1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* -*- mode: c; c-basic-offset: 8 -*- */
3
4 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
5 *
6 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
7 */
8
9 #ifndef _53C700_H
10 #define _53C700_H
11
12 #include <linux/interrupt.h>
13 #include <asm/io.h>
14
15 #include <scsi/scsi_device.h>
16 #include <scsi/scsi_cmnd.h>
17
18 /* Turn on for general debugging---too verbose for normal use */
19 #undef NCR_700_DEBUG
20 /* Debug the tag queues, checking hash queue allocation and deallocation
21 * and search for duplicate tags */
22 #undef NCR_700_TAG_DEBUG
23
24 #ifdef NCR_700_DEBUG
25 #define DEBUG(x) printk x
26 #define DDEBUG(prefix, sdev, fmt, a...) \
27 sdev_printk(prefix, sdev, fmt, ##a)
28 #define CDEBUG(prefix, scmd, fmt, a...) \
29 scmd_printk(prefix, scmd, fmt, ##a)
30 #else
31 #define DEBUG(x) do {} while (0)
32 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
33 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
34 #endif
35
36 /* The number of available command slots */
37 #define NCR_700_COMMAND_SLOTS_PER_HOST 64
38 /* The maximum number of Scatter Gathers we allow */
39 #define NCR_700_SG_SEGMENTS 32
40 /* The maximum number of luns (make this of the form 2^n) */
41 #define NCR_700_MAX_LUNS 32
42 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
43 /* Maximum number of tags the driver ever allows per device */
44 #define NCR_700_MAX_TAGS 16
45 /* Tag depth the driver starts out with (can be altered in sysfs) */
46 #define NCR_700_DEFAULT_TAGS 4
47 /* This is the default number of commands per LUN in the untagged case.
48 * two is a good value because it means we can have one command active and
49 * one command fully prepared and waiting
50 */
51 #define NCR_700_CMD_PER_LUN 2
52 /* magic byte identifying an internally generated REQUEST_SENSE command */
53 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42
54
55 struct NCR_700_Host_Parameters;
56
57 /* These are the externally used routines */
58 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
59 struct NCR_700_Host_Parameters *, struct device *);
60 int NCR_700_release(struct Scsi_Host *host);
61 irqreturn_t NCR_700_intr(int, void *);
62
63
64 enum NCR_700_Host_State {
65 NCR_700_HOST_BUSY,
66 NCR_700_HOST_FREE,
67 };
68
69 struct NCR_700_SG_List {
70 /* The following is a script fragment to move the buffer onto the
71 * bus and then link the next fragment or return */
72 #define SCRIPT_MOVE_DATA_IN 0x09000000
73 #define SCRIPT_MOVE_DATA_OUT 0x08000000
74 __u32 ins;
75 __u32 pAddr;
76 #define SCRIPT_NOP 0x80000000
77 #define SCRIPT_RETURN 0x90080000
78 };
79
80 struct NCR_700_Device_Parameters {
81 /* space for creating a request sense command. Really, except
82 * for the annoying SCSI-2 requirement for LUN information in
83 * cmnd[1], this could be in static storage */
84 unsigned char cmnd[MAX_COMMAND_SIZE];
85 __u8 depth;
86 struct scsi_cmnd *current_cmnd; /* currently active command */
87 };
88
89
90 /* The SYNC negotiation sequence looks like:
91 *
92 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
93 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTIATION
94 * If we get an SDTR reply, work out the SXFER parameters, squirrel
95 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
96 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
97 *
98 *
99 * 0:7 SXFER_REG negotiated value for this device
100 * 8:15 Current queue depth
101 * 16 negotiated SYNC flag
102 * 17 begin SYNC negotiation flag
103 * 18 device supports tag queueing */
104 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
105 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
106 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
107
NCR_700_get_sense_cmnd(struct scsi_device * SDp)108 static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
109 {
110 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
111
112 return hostdata->cmnd;
113 }
114
115 static inline void
NCR_700_set_depth(struct scsi_device * SDp,__u8 depth)116 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
117 {
118 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
119
120 hostdata->depth = depth;
121 }
122 static inline __u8
NCR_700_get_depth(struct scsi_device * SDp)123 NCR_700_get_depth(struct scsi_device *SDp)
124 {
125 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
126
127 return hostdata->depth;
128 }
129 static inline int
NCR_700_is_flag_set(struct scsi_device * SDp,__u32 flag)130 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
131 {
132 return (spi_flags(SDp->sdev_target) & flag) == flag;
133 }
134 static inline int
NCR_700_is_flag_clear(struct scsi_device * SDp,__u32 flag)135 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
136 {
137 return (spi_flags(SDp->sdev_target) & flag) == 0;
138 }
139 static inline void
NCR_700_set_flag(struct scsi_device * SDp,__u32 flag)140 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
141 {
142 spi_flags(SDp->sdev_target) |= flag;
143 }
144 static inline void
NCR_700_clear_flag(struct scsi_device * SDp,__u32 flag)145 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
146 {
147 spi_flags(SDp->sdev_target) &= ~flag;
148 }
149
150 enum NCR_700_tag_neg_state {
151 NCR_700_START_TAG_NEGOTIATION = 0,
152 NCR_700_DURING_TAG_NEGOTIATION = 1,
153 NCR_700_FINISHED_TAG_NEGOTIATION = 2,
154 };
155
156 static inline enum NCR_700_tag_neg_state
NCR_700_get_tag_neg_state(struct scsi_device * SDp)157 NCR_700_get_tag_neg_state(struct scsi_device *SDp)
158 {
159 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
160 }
161
162 static inline void
NCR_700_set_tag_neg_state(struct scsi_device * SDp,enum NCR_700_tag_neg_state state)163 NCR_700_set_tag_neg_state(struct scsi_device *SDp,
164 enum NCR_700_tag_neg_state state)
165 {
166 /* clear the slot */
167 spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
168 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
169 }
170
171 struct NCR_700_command_slot {
172 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
173 struct NCR_700_SG_List *pSG;
174 #define NCR_700_SLOT_MASK 0xFC
175 #define NCR_700_SLOT_MAGIC 0xb8
176 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
177 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
178 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
179 __u8 state;
180 #define NCR_700_FLAG_AUTOSENSE 0x01
181 __u8 flags;
182 __u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
183 int tag;
184 __u32 resume_offset;
185 struct scsi_cmnd *cmnd;
186 /* The pci_mapped address of the actual command in cmnd */
187 dma_addr_t pCmd;
188 __u32 temp;
189 /* if this command is a pci_single mapping, holds the dma address
190 * for later unmapping in the done routine */
191 dma_addr_t dma_handle;
192 /* historical remnant, now used to link free commands */
193 struct NCR_700_command_slot *ITL_forw;
194 };
195
196 struct NCR_700_Host_Parameters {
197 /* These must be filled in by the calling driver */
198 int clock; /* board clock speed in MHz */
199 void __iomem *base; /* the base for the port (copied to host) */
200 struct device *dev;
201 __u32 dmode_extra; /* adjustable bus settings */
202 __u32 dcntl_extra; /* adjustable bus settings */
203 __u32 ctest7_extra; /* adjustable bus settings */
204 __u32 differential:1; /* if we are differential */
205 #ifdef CONFIG_53C700_LE_ON_BE
206 /* This option is for HP only. Set it if your chip is wired for
207 * little endian on this platform (which is big endian) */
208 __u32 force_le_on_be:1;
209 #endif
210 __u32 chip710:1; /* set if really a 710 not 700 */
211 __u32 burst_length:4; /* set to 0 to disable 710 bursting */
212 __u32 noncoherent:1; /* needs to use non-coherent DMA */
213
214 /* NOTHING BELOW HERE NEEDS ALTERING */
215 __u32 fast:1; /* if we can alter the SCSI bus clock
216 speed (so can negiotiate sync) */
217 int sync_clock; /* The speed of the SYNC core */
218
219 __u32 *script; /* pointer to script location */
220 __u32 pScript; /* physical mem addr of script */
221
222 enum NCR_700_Host_State state; /* protected by state lock */
223 struct scsi_cmnd *cmd;
224 /* Note: pScript contains the single consistent block of
225 * memory. All the msgin, msgout and status are allocated in
226 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
227 * represents the total size of this area */
228 #define MSG_ARRAY_SIZE 8
229 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
230 __u8 *msgout;
231 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
232 __u8 *msgin;
233 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
234 __u8 *status;
235 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
236 struct NCR_700_command_slot *slots;
237 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
238 int saved_slot_position;
239 int command_slot_count; /* protected by state lock */
240 __u8 tag_negotiated;
241 __u8 rev;
242 __u8 reselection_id;
243 __u8 min_period;
244
245 /* Free list, singly linked by ITL_forw elements */
246 struct NCR_700_command_slot *free_list;
247 /* Completion for waited for ops, like reset, abort or
248 * device reset.
249 *
250 * NOTE: relies on single threading in the error handler to
251 * have only one outstanding at once */
252 struct completion *eh_complete;
253 };
254
255 /*
256 * 53C700 Register Interface - the offset from the Selected base
257 * I/O address */
258 #ifdef CONFIG_53C700_LE_ON_BE
259 #define bE (hostdata->force_le_on_be ? 0 : 3)
260 #define bSWAP (hostdata->force_le_on_be)
261 #define bEBus (!hostdata->force_le_on_be)
262 #elif defined(__BIG_ENDIAN)
263 #define bE 3
264 #define bSWAP 0
265 #elif defined(__LITTLE_ENDIAN)
266 #define bE 0
267 #define bSWAP 0
268 #else
269 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
270 #endif
271 #ifndef bEBus
272 #ifdef CONFIG_53C700_BE_BUS
273 #define bEBus 1
274 #else
275 #define bEBus 0
276 #endif
277 #endif
278 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
279 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
280
281 /* NOTE: These registers are in the LE register space only, the required byte
282 * swapping is done by the NCR_700_{read|write}[b] functions */
283 #define SCNTL0_REG 0x00
284 #define FULL_ARBITRATION 0xc0
285 #define PARITY 0x08
286 #define ENABLE_PARITY 0x04
287 #define AUTO_ATN 0x02
288 #define SCNTL1_REG 0x01
289 #define SLOW_BUS 0x80
290 #define ENABLE_SELECT 0x20
291 #define ASSERT_RST 0x08
292 #define ASSERT_EVEN_PARITY 0x04
293 #define SDID_REG 0x02
294 #define SIEN_REG 0x03
295 #define PHASE_MM_INT 0x80
296 #define FUNC_COMP_INT 0x40
297 #define SEL_TIMEOUT_INT 0x20
298 #define SELECT_INT 0x10
299 #define GROSS_ERR_INT 0x08
300 #define UX_DISC_INT 0x04
301 #define RST_INT 0x02
302 #define PAR_ERR_INT 0x01
303 #define SCID_REG 0x04
304 #define SXFER_REG 0x05
305 #define ASYNC_OPERATION 0x00
306 #define SODL_REG 0x06
307 #define SOCL_REG 0x07
308 #define SFBR_REG 0x08
309 #define SIDL_REG 0x09
310 #define SBDL_REG 0x0A
311 #define SBCL_REG 0x0B
312 /* read bits */
313 #define SBCL_IO 0x01
314 /*write bits */
315 #define SYNC_DIV_AS_ASYNC 0x00
316 #define SYNC_DIV_1_0 0x01
317 #define SYNC_DIV_1_5 0x02
318 #define SYNC_DIV_2_0 0x03
319 #define DSTAT_REG 0x0C
320 #define ILGL_INST_DETECTED 0x01
321 #define WATCH_DOG_INTERRUPT 0x02
322 #define SCRIPT_INT_RECEIVED 0x04
323 #define ABORTED 0x10
324 #define SSTAT0_REG 0x0D
325 #define PARITY_ERROR 0x01
326 #define SCSI_RESET_DETECTED 0x02
327 #define UNEXPECTED_DISCONNECT 0x04
328 #define SCSI_GROSS_ERROR 0x08
329 #define SELECTED 0x10
330 #define SELECTION_TIMEOUT 0x20
331 #define FUNCTION_COMPLETE 0x40
332 #define PHASE_MISMATCH 0x80
333 #define SSTAT1_REG 0x0E
334 #define SIDL_REG_FULL 0x80
335 #define SODR_REG_FULL 0x40
336 #define SODL_REG_FULL 0x20
337 #define SSTAT2_REG 0x0F
338 #define CTEST0_REG 0x14
339 #define BTB_TIMER_DISABLE 0x40
340 #define CTEST1_REG 0x15
341 #define CTEST2_REG 0x16
342 #define CTEST3_REG 0x17
343 #define CTEST4_REG 0x18
344 #define DISABLE_FIFO 0x00
345 #define SLBE 0x10
346 #define SFWR 0x08
347 #define BYTE_LANE0 0x04
348 #define BYTE_LANE1 0x05
349 #define BYTE_LANE2 0x06
350 #define BYTE_LANE3 0x07
351 #define SCSI_ZMODE 0x20
352 #define ZMODE 0x40
353 #define CTEST5_REG 0x19
354 #define MASTER_CONTROL 0x10
355 #define DMA_DIRECTION 0x08
356 #define CTEST7_REG 0x1B
357 #define BURST_DISABLE 0x80 /* 710 only */
358 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
359 #define DFP 0x08
360 #define EVP 0x04
361 #define CTEST7_TT1 0x02
362 #define DIFF 0x01
363 #define CTEST6_REG 0x1A
364 #define TEMP_REG 0x1C
365 #define DFIFO_REG 0x20
366 #define FLUSH_DMA_FIFO 0x80
367 #define CLR_FIFO 0x40
368 #define ISTAT_REG 0x21
369 #define ABORT_OPERATION 0x80
370 #define SOFTWARE_RESET_710 0x40
371 #define DMA_INT_PENDING 0x01
372 #define SCSI_INT_PENDING 0x02
373 #define CONNECTED 0x08
374 #define CTEST8_REG 0x22
375 #define LAST_DIS_ENBL 0x01
376 #define SHORTEN_FILTERING 0x04
377 #define ENABLE_ACTIVE_NEGATION 0x10
378 #define GENERATE_RECEIVE_PARITY 0x20
379 #define CLR_FIFO_710 0x04
380 #define FLUSH_DMA_FIFO_710 0x08
381 #define CTEST9_REG 0x23
382 #define DBC_REG 0x24
383 #define DCMD_REG 0x27
384 #define DNAD_REG 0x28
385 #define DIEN_REG 0x39
386 #define BUS_FAULT 0x20
387 #define ABORT_INT 0x10
388 #define INT_INST_INT 0x04
389 #define WD_INT 0x02
390 #define ILGL_INST_INT 0x01
391 #define DCNTL_REG 0x3B
392 #define SOFTWARE_RESET 0x01
393 #define COMPAT_700_MODE 0x01
394 #define SCRPTS_16BITS 0x20
395 #define EA_710 0x20
396 #define ASYNC_DIV_2_0 0x00
397 #define ASYNC_DIV_1_5 0x40
398 #define ASYNC_DIV_1_0 0x80
399 #define ASYNC_DIV_3_0 0xc0
400 #define DMODE_710_REG 0x38
401 #define DMODE_700_REG 0x34
402 #define BURST_LENGTH_1 0x00
403 #define BURST_LENGTH_2 0x40
404 #define BURST_LENGTH_4 0x80
405 #define BURST_LENGTH_8 0xC0
406 #define DMODE_FC1 0x10
407 #define DMODE_FC2 0x20
408 #define BW16 32
409 #define MODE_286 16
410 #define IO_XFER 8
411 #define FIXED_ADDR 4
412
413 #define DSP_REG 0x2C
414 #define DSPS_REG 0x30
415
416 /* Parameters to begin SDTR negotiations. Empirically, I find that
417 * the 53c700-66 cannot handle an offset >8, so don't change this */
418 #define NCR_700_MAX_OFFSET 8
419 /* Was hoping the max offset would be greater for the 710, but
420 * empirically it seems to be 8 also */
421 #define NCR_710_MAX_OFFSET 8
422 #define NCR_700_MIN_XFERP 1
423 #define NCR_710_MIN_XFERP 0
424 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
425
426 #define script_patch_32(h, script, symbol, value) \
427 { \
428 int i; \
429 dma_addr_t da = value; \
430 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
431 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
432 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
433 dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
434 DEBUG((" script, patching %s at %d to %pad\n", \
435 #symbol, A_##symbol##_used[i], &da)); \
436 } \
437 }
438
439 #define script_patch_32_abs(h, script, symbol, value) \
440 { \
441 int i; \
442 dma_addr_t da = value; \
443 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
444 (script)[A_##symbol##_used[i]] = bS_to_host(da); \
445 dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
446 DEBUG((" script, patching %s at %d to %pad\n", \
447 #symbol, A_##symbol##_used[i], &da)); \
448 } \
449 }
450
451 /* Used for patching the SCSI ID in the SELECT instruction */
452 #define script_patch_ID(h, script, symbol, value) \
453 { \
454 int i; \
455 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
456 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
457 val &= 0xff00ffff; \
458 val |= ((value) & 0xff) << 16; \
459 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
460 dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
461 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
462 #symbol, A_##symbol##_used[i], val)); \
463 } \
464 }
465
466 #define script_patch_16(h, script, symbol, value) \
467 { \
468 int i; \
469 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
470 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
471 val &= 0xffff0000; \
472 val |= ((value) & 0xffff); \
473 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
474 dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
475 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
476 #symbol, A_##symbol##_used[i], val)); \
477 } \
478 }
479
480
481 static inline __u8
NCR_700_readb(struct Scsi_Host * host,__u32 reg)482 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
483 {
484 const struct NCR_700_Host_Parameters *hostdata
485 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
486
487 return ioread8(hostdata->base + (reg^bE));
488 }
489
490 static inline __u32
NCR_700_readl(struct Scsi_Host * host,__u32 reg)491 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
492 {
493 const struct NCR_700_Host_Parameters *hostdata
494 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
495 __u32 value = bEBus ? ioread32be(hostdata->base + reg) :
496 ioread32(hostdata->base + reg);
497 #if 1
498 /* sanity check the register */
499 BUG_ON((reg & 0x3) != 0);
500 #endif
501
502 return value;
503 }
504
505 static inline void
NCR_700_writeb(__u8 value,struct Scsi_Host * host,__u32 reg)506 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
507 {
508 const struct NCR_700_Host_Parameters *hostdata
509 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
510
511 iowrite8(value, hostdata->base + (reg^bE));
512 }
513
514 static inline void
NCR_700_writel(__u32 value,struct Scsi_Host * host,__u32 reg)515 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
516 {
517 const struct NCR_700_Host_Parameters *hostdata
518 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
519
520 #if 1
521 /* sanity check the register */
522 BUG_ON((reg & 0x3) != 0);
523 #endif
524
525 bEBus ? iowrite32be(value, hostdata->base + reg):
526 iowrite32(value, hostdata->base + reg);
527 }
528
529 #endif
530