Searched refs:TILE_SPLIT (Results 1 – 16 of 16) sorted by relevance
81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v6_0_tiling_mode_table_init()430 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v6_0_tiling_mode_table_init()438 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()450 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()457 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v6_0_tiling_mode_table_init()465 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()473 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | in gfx_v6_0_tiling_mode_table_init()485 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()493 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()[all …]
69 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro2128 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()2136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v8_0_tiling_mode_table_init()2140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v8_0_tiling_mode_table_init()2144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2148 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2300 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v7_0_tiling_mode_table_init()1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v7_0_tiling_mode_table_init()1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v7_0_tiling_mode_table_init()1074 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1081 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1082 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1096 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1112 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1132 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
191 # define TILE_SPLIT(x) ((x) << 11) macro
1169 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1195 # define TILE_SPLIT(x) ((x) << 11) macro
1943 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1994 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2523 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2532 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2541 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in si_tiling_mode_table_init()2550 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2568 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2577 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2586 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2595 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()[all …]
2369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2373 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2381 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); in cik_tiling_mode_table_init()2385 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2396 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
1730 typedef enum TILE_SPLIT { enum1738 } TILE_SPLIT; typedef
3982 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_plane_buffer_attributes()