Searched refs:pll_post_div (Results 1 – 5 of 5) sorted by relevance
230 unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom; in nlm_xlp2_get_core_frequency() local250 pll_post_div = 2; in nlm_xlp2_get_core_frequency()253 pll_post_div = 4; in nlm_xlp2_get_core_frequency()256 pll_post_div = 8; in nlm_xlp2_get_core_frequency()259 pll_post_div = 16; in nlm_xlp2_get_core_frequency()263 pll_post_div = 1; in nlm_xlp2_get_core_frequency()268 denom = 3 * pll_post_div; in nlm_xlp2_get_core_frequency()310 u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx; in nlm_xlp2_get_pic_frequency() local406 pll_post_div = (ctrl_val0 >> 24) & 0x7; in nlm_xlp2_get_pic_frequency()411 switch (pll_post_div) { in nlm_xlp2_get_pic_frequency()[all …]
416 u32 pll_post_div; member
442 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in amdgpu_atombios_crtc_adjust_pll()852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
362 u32 pll_post_div; member
745 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()1098 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()