/kernel/linux/linux-5.10/drivers/mmc/host/ |
D | cavium.h | 37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off) 38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off) 39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off) 40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off) 41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off) 42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off) 43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off) 44 #define MIO_EMM_INT(x) (0x78 + x->reg_off) 45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off) 46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off) [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
D | dpu_hw_vbif.c | 59 u32 reg_off; in dpu_hw_set_mem_type() local 74 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; in dpu_hw_set_mem_type() 76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; in dpu_hw_set_mem_type() 79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type() 82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type() 90 u32 reg_off; in dpu_hw_set_limit_conf() local 94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf() 96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf() 98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf() 100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf() [all …]
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D | dpu_hw_catalog.c | 133 .reg_off = 0x2AC, .bit_off = 0}, 135 .reg_off = 0x2B4, .bit_off = 0}, 137 .reg_off = 0x2BC, .bit_off = 0}, 139 .reg_off = 0x2C4, .bit_off = 0}, 141 .reg_off = 0x2AC, .bit_off = 8}, 143 .reg_off = 0x2B4, .bit_off = 8}, 145 .reg_off = 0x2BC, .bit_off = 8}, 147 .reg_off = 0x2C4, .bit_off = 8}, 158 .reg_off = 0x2AC, .bit_off = 0}, 160 .reg_off = 0x2AC, .bit_off = 8}, [all …]
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D | dpu_hw_top.c | 95 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local 107 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl() 110 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl() 117 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
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D | dpu_hw_util.c | 63 u32 reg_off, in dpu_reg_write() argument 70 name, c->blk_off + reg_off, val); in dpu_reg_write() 71 writel_relaxed(val, c->base_off + c->blk_off + reg_off); in dpu_reg_write() 74 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) in dpu_reg_read() argument 76 return readl_relaxed(c->base_off + c->blk_off + reg_off); in dpu_reg_read()
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D | dpu_hw_util.h | 301 u32 reg_off, 304 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
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/kernel/linux/linux-5.10/drivers/pinctrl/ |
D | pinctrl-digicolor.c | 129 int bit_off, reg_off; in dc_set_mux() local 132 dc_client_sel(group, ®_off, &bit_off); in dc_set_mux() 134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux() 137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux() 147 int bit_off, reg_off; in dc_pmx_request_gpio() local 150 dc_client_sel(offset, ®_off, &bit_off); in dc_pmx_request_gpio() 152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio() 170 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local 176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input() 178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input() [all …]
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/kernel/linux/linux-5.10/drivers/clk/meson/ |
D | axg.c | 28 .reg_off = HHI_MPLL_CNTL, 33 .reg_off = HHI_MPLL_CNTL, 38 .reg_off = HHI_MPLL_CNTL, 43 .reg_off = HHI_MPLL_CNTL2, 48 .reg_off = HHI_MPLL_CNTL, 53 .reg_off = HHI_MPLL_CNTL, 92 .reg_off = HHI_SYS_PLL_CNTL, 97 .reg_off = HHI_SYS_PLL_CNTL, 102 .reg_off = HHI_SYS_PLL_CNTL, 107 .reg_off = HHI_SYS_PLL_CNTL, [all …]
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D | meson8-ddr.c | 28 .reg_off = AM_DDR_PLL_CNTL, 33 .reg_off = AM_DDR_PLL_CNTL, 38 .reg_off = AM_DDR_PLL_CNTL, 43 .reg_off = AM_DDR_PLL_CNTL, 48 .reg_off = AM_DDR_PLL_CNTL,
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D | g12a-aoclk.c | 121 .reg_off = AO_RTC_ALT_CLK_CNTL0, 126 .reg_off = AO_RTC_ALT_CLK_CNTL0, 131 .reg_off = AO_RTC_ALT_CLK_CNTL1, 136 .reg_off = AO_RTC_ALT_CLK_CNTL1, 141 .reg_off = AO_RTC_ALT_CLK_CNTL0, 212 .reg_off = AO_CEC_CLK_CNTL_REG0, 217 .reg_off = AO_CEC_CLK_CNTL_REG0, 222 .reg_off = AO_CEC_CLK_CNTL_REG1, 227 .reg_off = AO_CEC_CLK_CNTL_REG1, 232 .reg_off = AO_CEC_CLK_CNTL_REG0,
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D | parm.h | 25 u16 reg_off; member 34 regmap_read(map, p->reg_off, &val); in meson_parm_read() 41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
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D | gxbb.c | 88 .reg_off = HHI_MPLL_CNTL, 93 .reg_off = HHI_MPLL_CNTL, 98 .reg_off = HHI_MPLL_CNTL, 103 .reg_off = HHI_MPLL_CNTL2, 108 .reg_off = HHI_MPLL_CNTL, 113 .reg_off = HHI_MPLL_CNTL, 165 .reg_off = HHI_HDMI_PLL_CNTL, 170 .reg_off = HHI_HDMI_PLL_CNTL, 175 .reg_off = HHI_HDMI_PLL_CNTL, 180 .reg_off = HHI_HDMI_PLL_CNTL2, [all …]
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D | gxbb-aoclk.c | 88 .reg_off = AO_RTC_ALT_CLK_CNTL0, 93 .reg_off = AO_RTC_ALT_CLK_CNTL0, 98 .reg_off = AO_RTC_ALT_CLK_CNTL1, 103 .reg_off = AO_RTC_ALT_CLK_CNTL1, 108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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D | g12a.c | 32 .reg_off = HHI_FIX_PLL_CNTL0, 37 .reg_off = HHI_FIX_PLL_CNTL0, 42 .reg_off = HHI_FIX_PLL_CNTL0, 47 .reg_off = HHI_FIX_PLL_CNTL1, 52 .reg_off = HHI_FIX_PLL_CNTL0, 57 .reg_off = HHI_FIX_PLL_CNTL0, 101 .reg_off = HHI_SYS_PLL_CNTL0, 106 .reg_off = HHI_SYS_PLL_CNTL0, 111 .reg_off = HHI_SYS_PLL_CNTL0, 116 .reg_off = HHI_SYS_PLL_CNTL0, [all …]
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D | axg-aoclk.c | 102 .reg_off = AO_RTC_ALT_CLK_CNTL0, 107 .reg_off = AO_RTC_ALT_CLK_CNTL0, 112 .reg_off = AO_RTC_ALT_CLK_CNTL1, 117 .reg_off = AO_RTC_ALT_CLK_CNTL1, 122 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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D | meson8b.c | 67 .reg_off = HHI_MPLL_CNTL, 72 .reg_off = HHI_MPLL_CNTL, 77 .reg_off = HHI_MPLL_CNTL, 82 .reg_off = HHI_MPLL_CNTL2, 87 .reg_off = HHI_MPLL_CNTL, 92 .reg_off = HHI_MPLL_CNTL, 133 .reg_off = HHI_VID_PLL_CNTL, 138 .reg_off = HHI_VID_PLL_CNTL, 143 .reg_off = HHI_VID_PLL_CNTL, 148 .reg_off = HHI_VID_PLL_CNTL2, [all …]
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/kernel/linux/linux-5.10/drivers/irqchip/ |
D | irq-davinci-aintc.c | 82 unsigned int irq_off, reg_off, prio, shift; in davinci_aintc_init() local 125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; in davinci_aintc_init() 126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { in davinci_aintc_init() 129 davinci_aintc_writel(prio, reg_off); in davinci_aintc_init() 156 for (irq_off = 0, reg_off = 0; in davinci_aintc_init() 158 irq_off += 32, reg_off += 0x04) in davinci_aintc_init() 159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off, in davinci_aintc_init()
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/kernel/linux/linux-5.10/drivers/pinctrl/spear/ |
D | pinctrl-plgpio.c | 83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local 84 u32 val = readl_relaxed(reg_off); in is_plgpio_set() 92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local 93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set() 95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set() 101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset() local 102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset() 104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset() 323 void __iomem *reg_off; in plgpio_irq_set_type() local 340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); in plgpio_irq_set_type() [all …]
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/kernel/linux/linux-5.10/drivers/thermal/samsung/ |
D | exynos_tmu.c | 452 unsigned int reg_off, j; in exynos5433_tmu_set_trip_temp() local 456 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; in exynos5433_tmu_set_trip_temp() 459 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; in exynos5433_tmu_set_trip_temp() 463 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_temp() 466 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_temp() 472 unsigned int reg_off, j; in exynos5433_tmu_set_trip_hyst() local 476 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; in exynos5433_tmu_set_trip_hyst() 479 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; in exynos5433_tmu_set_trip_hyst() 483 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_hyst() 486 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_hyst() [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/ |
D | octeon_device.h | 740 #define octeon_write_csr(oct_dev, reg_off, value) \ argument 741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 743 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument 744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 746 #define octeon_read_csr(oct_dev, reg_off) \ argument 747 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 749 #define octeon_read_csr64(oct_dev, reg_off) \ argument 750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
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/kernel/linux/linux-5.10/arch/x86/kvm/ |
D | lapic.h | 160 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument 162 return *((u32 *) (apic->regs + reg_off)); in kvm_lapic_get_reg() 165 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val) in __kvm_lapic_set_reg() argument 167 *((u32 *) (regs + reg_off)) = val; in __kvm_lapic_set_reg() 170 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument 172 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
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/kernel/linux/linux-5.10/drivers/misc/habanalabs/goya/ |
D | goya.c | 908 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman() local 921 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman() 922 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman() 924 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman() 925 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman() 926 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman() 928 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman() 929 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman() 930 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); in goya_init_dma_qman() 931 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); in goya_init_dma_qman() [all …]
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/kernel/linux/linux-5.10/sound/soc/xilinx/ |
D | xlnx_i2s.c | 42 u32 reg_off, chan_id; in xlnx_i2s_hw_params() local 48 reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); in xlnx_i2s_hw_params() 49 writel(chan_id, base + reg_off); in xlnx_i2s_hw_params()
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
D | qcom_nandc.c | 808 int reg_off, const void *vaddr, in prep_bam_dma_desc_cmd() argument 822 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd() 828 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd() 894 int reg_off, const void *vaddr, int size, in prep_adm_dma_desc() argument 931 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc() 935 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc() 1047 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument 1053 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma() 1065 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument 1071 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma() [all …]
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/kernel/linux/linux-5.10/drivers/clk/ |
D | clk-stm32mp1.c | 329 u32 reg_off; member 340 u32 reg_off; member 348 u32 reg_off; member 391 gate_cfg->reg_off + base, in _clk_hw_register_gate() 422 div_cfg->reg_off + base, in _clk_hw_register_divider_table() 440 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux() 485 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux() 500 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux() 523 div->reg = cfg->div->reg_off + base; in _get_stm32_div() 546 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate() [all …]
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