Searched refs:AMDGPU_TILING_GET (Results 1 – 4 of 4) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 947 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in radv_amdgpu_winsys_bo_get_metadata()
948 md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); in radv_amdgpu_winsys_bo_get_metadata()
953 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_get_metadata()
955 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_get_metadata()
958 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in radv_amdgpu_winsys_bo_get_metadata()
959 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in radv_amdgpu_winsys_bo_get_metadata()
960 md->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in radv_amdgpu_winsys_bo_get_metadata()
961 md->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); in radv_amdgpu_winsys_bo_get_metadata()
962 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in radv_amdgpu_winsys_bo_get_metadata()
963 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in radv_amdgpu_winsys_bo_get_metadata()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.c | 80 #define AMDGPU_TILING_GET(value, field) \ macro
2625 surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in ac_surface_set_bo_metadata()
2627 AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); in ac_surface_set_bo_metadata()
2629 AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B); in ac_surface_set_bo_metadata()
2631 AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE); in ac_surface_set_bo_metadata()
2632 surf->u.gfx9.color.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); in ac_surface_set_bo_metadata()
2633 scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); in ac_surface_set_bo_metadata()
2637 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in ac_surface_set_bo_metadata()
2638 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in ac_surface_set_bo_metadata()
2639 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in ac_surface_set_bo_metadata()
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| /third_party/libdrm/include/drm/ |
| D | amdgpu_drm.h | 379 #define AMDGPU_TILING_GET(value, field) \ macro
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| /third_party/mesa3d/include/drm-uapi/ |
| D | amdgpu_drm.h | 383 #define AMDGPU_TILING_GET(value, field) \ macro
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