Searched refs:ANDN (Results 1 – 12 of 12) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | README.SIMD.rst | 58 holds for ANDN, OR, and XOR.
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | constants-loong64.h | 347 ANDN = 0x2dU << 15, enumerator
1085 case ANDN: in InstructionType()
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| D | assembler-loong64.cc | 1126 GenRegister(ANDN, rk, rj, rd); in andn()
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| /third_party/openssl/doc/man3/ |
| D | OPENSSL_ia32cap.pod | 91 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
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| /third_party/node/deps/v8/src/diagnostics/loong64/ |
| D | disasm-loong64.cc | 1064 case ANDN: in DecodeTypekOp17()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedBroadwell.td | 658 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
997 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
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| D | X86SchedHaswell.td | 921 def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
1007 def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
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| D | X86SchedSkylakeClient.td | 658 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
1023 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
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| D | X86SchedSkylakeServer.td | 671 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
1182 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
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| D | X86InstrArithmetic.td | 1271 // ANDN Instruction
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| D | X86InstrSSE.td | 2296 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp, SchedWriteFLogic>;
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| /third_party/node/deps/v8/src/execution/loong64/ |
| D | simulator-loong64.cc | 3525 case ANDN: in DecodeTypeOp17()
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