| /third_party/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-q-a32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-q-t32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-operand-imm16-t32.cc | 476 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-a32.cc | 523 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-t32.cc | 638 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 625 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 625 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 942 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 929 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 919 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 919 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 1159 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 1159 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 929 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32.cc | 1565 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
1577 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32.cc | 1563 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
1575 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 1160 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 222 case APSR_nzcvq: in GetName()
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| D | instructions-aarch32.h | 843 APSR_nzcvq = 0x08, enumerator
853 CPSR_f = APSR_nzcvq,
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