1 /******************************************************************************
2 * @file mpu_armv7.h
3 * @brief CMSIS MPU API for Armv7-M MPU
4 * @version V5.1.2
5 * @date 25. May 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV7_H
32 #define ARM_MPU_ARMV7_H
33
34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62
63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69
70 /** MPU Region Base Address Register Value
71 *
72 * \param Region The region to be configured, number 0 to 15.
73 * \param BaseAddress The base address for the region.
74 */
75 #define ARM_MPU_RBAR(Region, BaseAddress) \
76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 ((Region) & MPU_RBAR_REGION_Msk) | \
78 (MPU_RBAR_VALID_Msk))
79
80 /**
81 * MPU Memory Access Attributes
82 *
83 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 * \param IsShareable Region is shareable between multiple bus masters.
85 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 */
88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93
94 /**
95 * MPU Region Attribute and Size Register Value
96 *
97 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 * \param SubRegionDisable Sub-region disable field.
101 * \param Size Region size of the region to be configured, for example 4K, 8K.
102 */
103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
107 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
108 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
109 (((MPU_RASR_ENABLE_Msk))))
110
111 /**
112 * MPU Region Attribute and Size Register Value
113 *
114 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
115 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
116 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
117 * \param IsShareable Region is shareable between multiple bus masters.
118 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
119 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
120 * \param SubRegionDisable Sub-region disable field.
121 * \param Size Region size of the region to be configured, for example 4K, 8K.
122 */
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
124 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
125
126 /**
127 * MPU Memory Access Attribute for strongly ordered memory.
128 * - TEX: 000b
129 * - Shareable
130 * - Non-cacheable
131 * - Non-bufferable
132 */
133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
134
135 /**
136 * MPU Memory Access Attribute for device memory.
137 * - TEX: 000b (if shareable) or 010b (if non-shareable)
138 * - Shareable or non-shareable
139 * - Non-cacheable
140 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
141 *
142 * \param IsShareable Configures the device memory as shareable or non-shareable.
143 */
144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
145
146 /**
147 * MPU Memory Access Attribute for normal memory.
148 * - TEX: 1BBb (reflecting outer cacheability rules)
149 * - Shareable or non-shareable
150 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
151 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
152 *
153 * \param OuterCp Configures the outer cache policy.
154 * \param InnerCp Configures the inner cache policy.
155 * \param IsShareable Configures the memory as shareable or non-shareable.
156 */
157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
158
159 /**
160 * MPU Memory Access Attribute non-cacheable policy.
161 */
162 #define ARM_MPU_CACHEP_NOCACHE 0U
163
164 /**
165 * MPU Memory Access Attribute write-back, write and read allocate policy.
166 */
167 #define ARM_MPU_CACHEP_WB_WRA 1U
168
169 /**
170 * MPU Memory Access Attribute write-through, no write allocate policy.
171 */
172 #define ARM_MPU_CACHEP_WT_NWA 2U
173
174 /**
175 * MPU Memory Access Attribute write-back, no write allocate policy.
176 */
177 #define ARM_MPU_CACHEP_WB_NWA 3U
178
179
180 /**
181 * Struct for a single MPU Region
182 */
183 typedef struct {
184 uint32_t RBAR; //!< The region base address register value (RBAR)
185 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
186 } ARM_MPU_Region_t;
187
188 /** Enable the MPU.
189 * \param MPU_Control Default access permissions for unconfigured regions.
190 */
ARM_MPU_Enable(uint32_t MPU_Control)191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
192 {
193 __DMB();
194 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
195 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
197 #endif
198 __DSB();
199 __ISB();
200 }
201
202 /** Disable the MPU.
203 */
ARM_MPU_Disable(void)204 __STATIC_INLINE void ARM_MPU_Disable(void)
205 {
206 __DMB();
207 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
209 #endif
210 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
211 __DSB();
212 __ISB();
213 }
214
215 /** Clear and disable the given MPU region.
216 * \param rnr Region number to be cleared.
217 */
ARM_MPU_ClrRegion(uint32_t rnr)218 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
219 {
220 MPU->RNR = rnr;
221 MPU->RASR = 0U;
222 }
223
224 /** Configure an MPU region.
225 * \param rbar Value for RBAR register.
226 * \param rasr Value for RASR register.
227 */
ARM_MPU_SetRegion(uint32_t rbar,uint32_t rasr)228 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
229 {
230 MPU->RBAR = rbar;
231 MPU->RASR = rasr;
232 }
233
234 /** Configure the given MPU region.
235 * \param rnr Region number to be configured.
236 * \param rbar Value for RBAR register.
237 * \param rasr Value for RASR register.
238 */
ARM_MPU_SetRegionEx(uint32_t rnr,uint32_t rbar,uint32_t rasr)239 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
240 {
241 MPU->RNR = rnr;
242 MPU->RBAR = rbar;
243 MPU->RASR = rasr;
244 }
245
246 /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
247 * \param dst Destination data is copied to.
248 * \param src Source data is copied from.
249 * \param len Amount of data words to be copied.
250 */
ARM_MPU_OrderedMemcpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)251 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
252 {
253 uint32_t i;
254 for (i = 0U; i < len; ++i)
255 {
256 dst[i] = src[i];
257 }
258 }
259
260 /** Load the given number of MPU regions from a table.
261 * \param table Pointer to the MPU configuration table.
262 * \param cnt Amount of regions to be configured.
263 */
ARM_MPU_Load(ARM_MPU_Region_t const * table,uint32_t cnt)264 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
265 {
266 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
267 while (cnt > MPU_TYPE_RALIASES) {
268 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
269 table += MPU_TYPE_RALIASES;
270 cnt -= MPU_TYPE_RALIASES;
271 }
272 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
273 }
274
275 #endif
276