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Searched refs:AddrBaseReg (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
217 assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
DX86OptimizeLEAs.cpp194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
460 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
466 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
561 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
DX86AsmPrinter.cpp285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
322 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
372 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
DX86FixupLEAs.cpp357 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
450 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
486 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
536 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
DX86CallFrameOptimization.cpp427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
DX86InstrInfo.h116 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
DX86SpeculativeLoadHardening.cpp1713 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1786 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
2184 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
DX86AvoidStoreForwardingBlocks.cpp300 return MI->getOperand(AddrOffset + X86::AddrBaseReg); in getBaseOperand()
DX86InstrInfo.cpp195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && in isFrameOperand()
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); in isFrameOperand()
600 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
605 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
625 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
627 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
3202 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandWithOffset()
5925 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || in areLoadsFromSameBasePtr()
DX86MCInstLower.cpp355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in SimplifyShortMoveForm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand()
375 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
879 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
925 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
941 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
958 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
985 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1210 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in determineREXPrefix()
[all …]
DX86ATTInstPrinter.cpp388 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
409 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
DX86IntelInstPrinter.cpp346 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
358 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
DX86BaseInfo.h32 AddrBaseReg = 0, enumerator
DX86AsmBackend.cpp314 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg; in isRIPRelative()
DX86MCTargetDesc.cpp531 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()