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Searched refs:AddrReg (Results 1 – 23 of 23) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp240 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
251 .addReg(AddrReg); in doAtomicBinOpExpansion()
265 .addReg(AddrReg) in doAtomicBinOpExpansion()
302 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local
317 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
350 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
442 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local
457 .addReg(AddrReg); in expandAtomicMinMaxOp()
509 .addReg(AddrReg) in expandAtomicMinMaxOp()
554 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in ExpandStore()
71 .addReg(AddrReg) in ExpandStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp117 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
121 return AddrReg; in getStackAddress()
243 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
245 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
246 return AddrReg; in getStackAddress()
DX86SpeculativeLoadHardening.cpp1156 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1158 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg) in tracePredStateThroughIndirectBranches()
1169 .addReg(AddrReg, RegState::Kill); in tracePredStateThroughIndirectBranches()
DX86InstructionSelector.cpp1453 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); in materializeFP() local
1454 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg) in materializeFP()
1463 AddrReg) in materializeFP()
DX86FastISel.cpp3793 unsigned AddrReg = createResultReg(&X86::GR64RegClass); in X86MaterializeFP() local
3795 AddrReg) in X86MaterializeFP()
3799 addDirectMem(MIB, AddrReg); in X86MaterializeFP()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp108 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
112 return AddrReg; in getStackAddress()
302 Register AddrReg = in getStackAddress() local
304 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
306 return AddrReg; in getStackAddress()
DARMExpandPseudoInsts.cpp940 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP() local
969 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
993 .addReg(AddrReg); in ExpandCMP_SWAP()
1059 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP_64() local
1087 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1116 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
DARMFastISel.cpp1334 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1335 if (AddrReg == 0) return false; in SelectIndirectBr()
1341 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp1125 unsigned AddrReg; in buildIndirectWrite() local
1128 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1129 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1130 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1131 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1138 AddrReg, ValueReg) in buildIndirectWrite()
1157 unsigned AddrReg; in buildIndirectRead() local
1160 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1161 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1162 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
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DSILoadStoreOptimizer.cpp131 const MachineOperand *AddrReg[5]; member
138 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
139 if (AddrReg[i]->isImm() != AddrRegNext.isImm() || in hasSameBaseAddress()
140 AddrReg[i]->getImm() != AddrRegNext.getImm()) { in hasSameBaseAddress()
148 if (AddrReg[i]->getReg() != AddrRegNext.getReg() || in hasSameBaseAddress()
149 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) { in hasSameBaseAddress()
158 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
548 AddrReg[i] = &I->getOperand(AddrIdx[i]); in setMI()
958 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
988 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
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DAMDGPUCallLowering.cpp87 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
89 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
91 return AddrReg; in getStackAddress()
DSIInstrInfo.cpp330 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandWithOffset() local
331 if (AddrReg && !AddrReg->isFI()) in getMemOperandWithOffset()
347 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandWithOffset() local
348 if (!AddrReg) in getMemOperandWithOffset()
353 BaseOp = AddrReg; in getMemOperandWithOffset()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp504 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
518 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
572 .addReg(AddrReg) in optimizeLdStInterleave()
612 .addReg(AddrReg) in optimizeLdStInterleave()
617 .addReg(AddrReg) in optimizeLdStInterleave()
DAArch64ExpandPseudoInsts.cpp186 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
208 .addReg(AddrReg); in expandCMP_SWAP()
225 .addReg(AddrReg); in expandCMP_SWAP()
266 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
289 .addReg(AddrReg); in expandCMP_SWAP_128()
318 .addReg(AddrReg); in expandCMP_SWAP_128()
DAArch64CallLowering.cpp65 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); in getStackAddress() local
66 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
68 return AddrReg; in getStackAddress()
162 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
166 return AddrReg; in getStackAddress()
DAArch64FastISel.cpp231 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2090 unsigned AddrReg, in emitStoreRelease() argument
2103 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2106 .addReg(AddrReg) in emitStoreRelease()
2230 unsigned AddrReg = getRegForValue(PtrV); in selectStore() local
2231 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2552 unsigned AddrReg = getRegForValue(BI->getOperand(0)); in selectIndirectBr() local
2553 if (AddrReg == 0) in selectIndirectBr()
2558 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
2559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg); in selectIndirectBr()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp195 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); in getStackAddress() local
196 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
198 return AddrReg; in getStackAddress()
301 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
310 return AddrReg; in getStackAddress()
DMipsISelLowering.cpp2550 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; in lowerEH_RETURN() local
2552 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); in lowerEH_RETURN()
2555 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), in lowerEH_RETURN()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1857 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1858 if (AddrReg == 0) in SelectIndirectBr()
1862 .addReg(AddrReg); in SelectIndirectBr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp740 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); in printInst() local
741 O << ", [" << getRegisterName(AddrReg) << ']'; in printInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2913 Register AddrReg = MI.getOperand(1).getReg(); in reduceLoadStoreWidth() local
2933 const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits()); in reduceLoadStoreWidth()
2951 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); in reduceLoadStoreWidth()