| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 225 case RISCV::BLT: in getOppositeBranchOpcode()
228 return RISCV::BLT; in getOppositeBranchOpcode()
442 case RISCV::BLT: in isBranchOffsetInRange()
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| D | RISCVInstrInfo.td | 392 def BLT : BranchCC_rri<0b100, "blt">;
618 (BLT GPR:$rs, X0, simm13_lsb0:$offset)>;
620 (BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
627 (BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
881 def : BccPat<setlt, BLT>;
892 def : BccSwapPat<setgt, BLT>;
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| D | RISCVISelLowering.cpp | 373 return RISCV::BLT; in getBranchOpcodeForIntCondCode()
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| /third_party/skia/third_party/externals/sfntly/java/src/com/google/typography/font/sfntly/table/opentype/ |
| D | LanguageTag.java | 52 BLT("Balti", "bft"), enumConstant
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | constants-loong64.h | 243 BLT = 0x18U << 26, enumerator
943 case BLT: in InstructionType()
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| D | assembler-loong64.cc | 312 opcode == BNE || opcode == BLT || opcode == BGE || in IsBranch()
656 case BLT: in BranchOffset()
991 GenBJ(BLT, rj, rd, offset); in blt()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.4.rst | 79 - intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint
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| D | 18.1.8.rst | 146 - i965/miptree: Use the correct BLT pitch
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| D | 10.5.1.rst | 128 - i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.
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| D | 7.10.rst | 1383 - i965: Add support for using the BLT ring on gen6.
2848 - i965: use BLT to clear buffer if possible on Sandybridge
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| D | 22.0.0.rst | 1052 - intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint
2492 - iris: Create an IRIS_BATCH_BLITTER for using the BLT command streamer
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| D | 21.3.0.rst | 1132 - crocus: align staging resource pitch on gen4/5 to allow BLT usage.
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| D | comc597.mme.h | 532 MME_INSN(0, BLT, ZERO, R5, ZERO, (2<<14)|0x000e, NONE, NONE,
632 MME_INSN(0, BLT, ZERO, R5, ZERO, (2<<14)|0x000f, NONE, NONE,
742 MME_INSN(0, BLT, ZERO, R9, R8, (2<<14)|0x000e, NONE, NONE,
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| /third_party/python/Modules/ |
| D | Setup | 274 # specific extension (e.g. Tix or BLT), leave the corresponding line
293 # *** Uncomment and edit for BLT extension only:
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 508 case Mips::BLT: in getEquivalentCompactForm()
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| D | MipsInstrInfo.td | 2913 def BLT : CondBranchPseudo<"blt">;
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeRISCV_common.c | 87 #define BLT (F3(0x4) | OPC(0x63)) macro
1066 …FAIL_IF(push_inst(compiler, BLT | RS1(TMP_REG2) | RS2(TMP_ZERO) | ((sljit_ins)(2 * SSIZE_OF(ins)) … in emit_clz_ctz()
2469 inst = BLT | RS1(src1) | RS2(src2) | BRANCH_LENGTH; in sljit_emit_cmp()
2475 inst = BLT | RS1(src2) | RS2(src1) | BRANCH_LENGTH; in sljit_emit_cmp()
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| /third_party/node/deps/v8/src/diagnostics/loong64/ |
| D | disasm-loong64.cc | 640 case BLT: in DecodeTypekOp6()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2407 case Mips::BLT: in tryExpandInstruction()
3891 PseudoOpcode = Mips::BLT; in expandCondBranches()
3946 case Mips::BLT: in expandCondBranches()
4004 if (PseudoOpcode == Mips::BLT) { in expandCondBranches()
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| /third_party/rust/crates/memchr/bench/data/sliceslice/ |
| D | words.txt | 413 BLT
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| /third_party/node/deps/v8/src/execution/loong64/ |
| D | simulator-loong64.cc | 2604 case BLT: in DecodeTypeOp6()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 1548 268459523U, // BLT
4302 0U, // BLT
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| D | MipsGenMCCodeEmitter.inc | 9782 CEFBS_None, // BLT = 307
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| D | MipsGenInstrInfo.inc | 322 BLT = 307,
5168 …UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #307 = BLT
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| D | MipsGenAsmMatcher.inc | 5764 …{ 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, {…
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