Searched refs:BLTU (Results 1 – 16 of 16) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 229 case RISCV::BLTU: in getOppositeBranchOpcode()
232 return RISCV::BLTU; in getOppositeBranchOpcode()
444 case RISCV::BLTU: in isBranchOffsetInRange()
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| D | RISCVInstrInfo.td | 394 def BLTU : BranchCC_rri<0b110, "bltu">;
631 (BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
883 def : BccPat<setult, BLTU>;
894 def : BccSwapPat<setugt, BLTU>;
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| D | RISCVISelLowering.cpp | 377 return RISCV::BLTU; in getBranchOpcodeForIntCondCode()
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | constants-loong64.h | 245 BLTU = 0x1aU << 26, enumerator
945 case BLTU: in InstructionType()
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| D | assembler-loong64.cc | 313 opcode == BLTU || opcode == BGEU; in IsBranch()
658 case BLTU: in BranchOffset()
999 GenBJ(BLTU, rj, rd, offset); in bltu()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 512 case Mips::BLTU: in getEquivalentCompactForm()
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| D | MipsInstrInfo.td | 2917 def BLTU : CondBranchPseudo<"bltu">;
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeRISCV_common.c | 89 #define BLTU (F3(0x6) | OPC(0x63)) macro
2457 inst = BLTU | RS1(src1) | RS2(src2) | BRANCH_LENGTH; in sljit_emit_cmp()
2463 inst = BLTU | RS1(src2) | RS2(src1) | BRANCH_LENGTH; in sljit_emit_cmp()
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| /third_party/node/deps/v8/src/diagnostics/loong64/ |
| D | disasm-loong64.cc | 646 case BLTU: in DecodeTypekOp6()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| D | comc597.mme.h | 755 MME_INSN(0, BLTU, ZERO, R1, R2, (1<<14)|0x0002, NONE, NONE,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2411 case Mips::BLTU: in tryExpandInstruction()
3903 PseudoOpcode = Mips::BLTU; in expandCondBranches()
3947 case Mips::BLTU: in expandCondBranches()
3953 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
4045 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { in expandCondBranches()
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| /third_party/node/deps/v8/src/execution/loong64/ |
| D | simulator-loong64.cc | 2614 case BLTU: in DecodeTypeOp6()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 1552 268459758U, // BLTU
4306 0U, // BLTU
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| D | MipsGenMCCodeEmitter.inc | 9786 CEFBS_None, // BLTU = 311
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| D | MipsGenInstrInfo.inc | 326 BLTU = 311,
5172 …nmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #311 = BLTU
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| D | MipsGenAsmMatcher.inc | 5771 …{ 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None,…
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