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Searched refs:BRW_ARF_NULL (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c174 brw_inst_dst_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; in dst_is_null()
182 brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; in src0_is_null()
189 brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; in src1_is_null()
427 brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL, in send_restrictions()
1969 reg != BRW_ARF_NULL) || in special_requirements_for_handling_double_precision_data_types()
1971 dst_reg != BRW_ARF_NULL), in special_requirements_for_handling_double_precision_data_types()
2009 reg != BRW_ARF_NULL && !(reg >= BRW_ARF_ACCUMULATOR && reg < BRW_ARF_FLAG)) || in special_requirements_for_handling_double_precision_data_types()
2011 dst_reg != BRW_ARF_NULL && dst_reg != BRW_ARF_ACCUMULATOR), in special_requirements_for_handling_double_precision_data_types()
2117 brw_inst_dst_da_reg_nr(devinfo, inst) != BRW_ARF_NULL, in instruction_restrictions()
Dbrw_reg.h821 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); in brw_null_reg()
827 return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); in brw_null_vec()
Dbrw_eu_defines.h1028 #define BRW_ARF_NULL 0x00 macro
Dbrw_shader.cpp850 return file == ARF && nr == BRW_ARF_NULL; in is_null()
Dbrw_eu_emit.c57 if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) { in gfx6_resolve_implied_move()
104 dest.nr == BRW_ARF_NULL && in brw_set_dest()
2007 dest.nr == BRW_ARF_NULL) { in brw_CMP()
2037 dest.nr == BRW_ARF_NULL) { in brw_CMPN()
Dbrw_vec4.cpp1352 case BRW_ARF_NULL: in dump_instruction()
1446 case BRW_ARF_NULL: in dump_instruction()
Dbrw_disasm.c842 case BRW_ARF_NULL: in reg()
Dbrw_fs_generator.cpp329 dst.nr == BRW_ARF_NULL; in generate_send()
Dbrw_fs.cpp5709 case BRW_ARF_NULL: in dump_instruction()
5810 case BRW_ARF_NULL: in dump_instruction()