Searched refs:BRW_OPCODE_NOP (Results 1 – 12 of 12) sorted by relevance
/third_party/mesa3d/src/intel/compiler/ |
D | brw_vec4_dead_code_eliminate.cpp | 120 inst->opcode = BRW_OPCODE_NOP; in dead_code_eliminate() 135 inst->opcode = BRW_OPCODE_NOP; in dead_code_eliminate() 157 if (inst->opcode == BRW_OPCODE_NOP) { in dead_code_eliminate()
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D | brw_fs_dead_code_eliminate.cpp | 108 inst->opcode = BRW_OPCODE_NOP; in dead_code_eliminate() 124 if (inst->opcode == BRW_OPCODE_NOP) { in dead_code_eliminate()
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D | brw_fs_register_coalesce.cpp | 208 inst->opcode = BRW_OPCODE_NOP; in register_coalesce() 284 mov[i]->opcode = BRW_OPCODE_NOP; in register_coalesce() 332 if (inst->opcode == BRW_OPCODE_NOP) { in register_coalesce()
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D | brw_eu.c | 704 { BRW_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) }, 705 { BRW_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) }
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D | brw_eu_defines.h | 262 BRW_OPCODE_NOP, enumerator
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D | brw_shader.cpp | 1096 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) || in writes_accumulator_implicitly()
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D | brw_disasm.c | 1955 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) { in brw_disassemble_inst() 2452 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) { in brw_disassemble_inst()
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D | brw_ir_performance.cpp | 331 case BRW_OPCODE_NOP: in instruction_desc()
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D | brw_eu_emit.c | 1335 brw_inst *insn = next_insn(p, BRW_OPCODE_NOP); in brw_NOP() 1337 brw_inst_set_opcode(p->isa, insn, BRW_OPCODE_NOP); in brw_NOP()
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D | brw_eu_compact.c | 2660 devinfo, align, brw_opcode_encode(p->isa, BRW_OPCODE_NOP)); in brw_compact_instructions()
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D | brw_fs.cpp | 95 init(BRW_OPCODE_NOP, 8, dst, NULL, 0); in fs_inst()
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/third_party/mesa3d/src/intel/tools/ |
D | i965_lex.l | 106 nop { yylval.integer = BRW_OPCODE_NOP; return NOP; }
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