Home
last modified time | relevance | path

Searched refs:Broadwell (Results 1 – 22 of 22) sorted by relevance

/third_party/mesa3d/docs/relnotes/
D10.2.4.rst72 - i965: Add auxiliary surface field #defines for Broadwell.
76 - i965: Don't copy propagate abs into Broadwell logic instructions.
81 - i965: Add plumbing for Broadwell's auxiliary surface support.
82 - i965: Drop SINT workaround for CMS layout on Broadwell.
83 - i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.
85 - i965: Enable compressed multisample support (CMS) on Broadwell.
D10.2.5.rst102 - i965: Add auxiliary surface field #defines for Broadwell.
111 - i965: Don't copy propagate abs into Broadwell logic instructions.
116 - i965: Add plumbing for Broadwell's auxiliary surface support.
117 - i965: Drop SINT workaround for CMS layout on Broadwell.
118 - i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.
120 - i965: Enable compressed multisample support (CMS) on Broadwell.
124 - i965/fs: Set LastRT on the final FB write on Broadwell.
D10.2.3.rst62 - i965: Don't emit SURFACE_STATEs for gather workarounds on Broadwell.
63 - i965: Include marketing names for Broadwell GPUs.
64 - i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.
D10.2.2.rst123 - i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.
124 - i965: Drop Broadwell perf_debugs about missing MOCS that aren't
127 - i965/vec4: Use the sampler for pull constant loads on Broadwell.
128 - i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.
D13.0.5.rst145 - isl/formats: Only advertise sampling for A4B4G4R4 on Broadwell
D19.1.0.rst1913 - intel/compiler: fix ddy for half-float in Broadwell
3209 - iris: Fill out brw_image_params for storage images on Broadwell
3211 - iris: Leave a comment about why Broadwell images are broken
3218 - iris: Fix Broadwell WaDividePSInvocationCountBy4
D19.3.0.rst2121 - iris: Implement the Broadwell NP Z PMA Stall Fix
/third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/
Ddriver_utils.cpp50 const uint32_t Broadwell[] = {0x1602, 0x1606, 0x160A, 0x160B, 0x160D, 0x160E, variable
110 return std::find(std::begin(Broadwell), std::end(Broadwell), DeviceId) != std::end(Broadwell); in IsBroadwell()
/third_party/mesa3d/docs/isl/
Dccs.rst14 The documentation for Ivy Bridge through Broadwell overloads the term MCS for
84 …Broadwell X :math:`u_6` :math:`u_5` :math:`u_4` :math:`v_7` :math:`v_6` :math:…
85 …Broadwell Y :math:`u_6` :math:`u_5` :math:`u_4` :math:`v_7` :math:`v_6` :math:…
92 Starting with Broadwell, fast-clears and color compression can be used on
94 layed out like any other surface. The Broadwell and Sky Lake PRMs describe
97 Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676):
103 Broadwell PRM Vol 2d, "RENDER_SURFACE_STATE" (p. 279):
132 On Broadwell, each miplevel in the CCS is aligned to a cache-line pair
139 TODO: More than just 32bpp formats on Broadwell!
150 bit-per-pixel on Ivy Bridge through Broadwell and 2 bits-per-pixel on Skylake
Dunits.rst28 Broadwell and earlier, QPitch field in :c:expr:`RENDER_SURFACE_STATE` was in
37 of elements. On Broadwell and earlier, we have to multiply by the block size
Daux-surf-comp.rst12 Broadwell and later. For this scheme, the auxiliary surface stores a single
Dtiling.rst54 on top of the tiling format. This has been removed starting with Broadwell
55 because, as it says in the Broadwell PRM Vol 5 "Tiling Algorithm" (p. 17):
/third_party/alsa-utils/bat/tests/asound_state/
DMakefile.am1 alsabat_cfg_files = asound.state.Broadwell \
/third_party/mesa3d/src/intel/isl/
DREADME102 ISL acquired the term 'surface element' from the Broadwell PRM [1], which
112 [1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >>
Disl_format_layout.csv26 # For the official list, see Broadwell PRM: Volume 2b: Command Reference:
/third_party/mesa3d/docs/
Dsourcetree.rst83 - **iris** - Driver for Intel gen 8 (Broadwell) and newer.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SchedBroadwell.td1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
9 // This file defines the machine model for Broadwell to support instruction
32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
1610 // section "Haswell and Broadwell Pipeline" > "Register allocation and
DX86.td585 // Broadwell
DX86SchedHaswell.td1863 // section "Haswell and Broadwell Pipeline" > "Register allocation and
/third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/gl/glx/
DFBConfigCompatibility.md204 - the open source Intel (Broadwell) Mesa driver
/third_party/node/deps/openssl/openssl/
DCHANGES.md3630 like Intel Broadwell (5th generation) and later or AMD Ryzen.
3750 There is a carry propagating bug in the Broadwell-specific Montgomery
5381 like Intel Broadwell (5th generation) and later or AMD Ryzen.
5441 There is a carry propagating bug in the Broadwell-specific Montgomery
/third_party/openssl/
DCHANGES.md3568 like Intel Broadwell (5th generation) and later or AMD Ryzen.
3688 There is a carry propagating bug in the Broadwell-specific Montgomery
5319 like Intel Broadwell (5th generation) and later or AMD Ryzen.
5379 There is a carry propagating bug in the Broadwell-specific Montgomery