Searched refs:CIK_UCONFIG_REG_END (Results 1 – 6 of 6) sorted by relevance
145 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()155 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()173 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()191 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_perfctr_reg()
183 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()199 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
34 #define CIK_UCONFIG_REG_END 0x00038000 macro
37 #define CIK_UCONFIG_REG_END 0x00040000 macro44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
139 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \156 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
95 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()