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Searched refs:DMA (Results 1 – 25 of 66) sorted by relevance

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/third_party/EGL/extensions/NV/
DEGL_NV_stream_dma.txt46 This extension provides the framework for performing DMA transfers
53 through sockets is slower compared to DMA transfers. Since DMA
56 utilize DMA channels to perform buffer copies.
81 DMA server identifier as defined by the platform.
96 created, and indicates whether the DMA channels have to be used to
100 A value of EGL_TRUE indicates that EGL has to use DMA channels to
103 If EGL_FALSE is specified, DMA channels will not be utilized for
110 indicates the server, which must be contacted to handle DMA
117 1. What happens when application requests DMA copy using
120 access to DMA channels?
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/third_party/mesa3d/src/imagination/vulkan/pds/
Dpvr_xgl_pds.c123 const struct pvr_pds_vertex_dma *DMA, in pvr_write_pds_const_map_entry_vertex_attribute_address() argument
128 DMA->size_in_dwords, in pvr_write_pds_const_map_entry_vertex_attribute_address()
129 DMA->stride, in pvr_write_pds_const_map_entry_vertex_attribute_address()
130 DMA->offset, in pvr_write_pds_const_map_entry_vertex_attribute_address()
131 DMA->binding_index); in pvr_write_pds_const_map_entry_vertex_attribute_address()
143 robust_attribute_entry->binding_index = DMA->binding_index; in pvr_write_pds_const_map_entry_vertex_attribute_address()
145 DMA->component_size_in_bytes; in pvr_write_pds_const_map_entry_vertex_attribute_address()
146 robust_attribute_entry->offset = DMA->offset; in pvr_write_pds_const_map_entry_vertex_attribute_address()
147 robust_attribute_entry->stride = DMA->stride; in pvr_write_pds_const_map_entry_vertex_attribute_address()
148 robust_attribute_entry->size_in_dwords = DMA->size_in_dwords; in pvr_write_pds_const_map_entry_vertex_attribute_address()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DMemorySSA.h285 MemoryUseOrDef(LLVMContext &C, MemoryAccess *DMA, unsigned Vty,
290 setDefiningAccess(DMA);
300 void setDefiningAccess(MemoryAccess *DMA, bool Optimized = false,
303 setOperand(0, DMA);
306 setOptimized(DMA);
324 MemoryUse(LLVMContext &C, MemoryAccess *DMA, Instruction *MI, BasicBlock *BB)
325 : MemoryUseOrDef(C, DMA, MemoryUseVal, deleteMe, MI, BB,
337 void setOptimized(MemoryAccess *DMA) {
338 OptimizedID = DMA->getID();
339 setOperand(0, DMA);
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/third_party/mesa3d/docs/relnotes/
D9.1.1.rst57 Corruption with DMA ring on cayman
88 - r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
172 - r600g: use async DMA with a non-zero src offset
176 - r600g: pad the DMA CS to a multiple of 8 dwords
D19.2.3.rst142 - svga: Fix banded DMA upload unmap
143 - winsys/svga: Limit the maximum DMA hardware buffer size
D17.0.2.rst59 - radv: Emit cache flushes before CP DMA.
60 - Revert "radv: Emit cache flushes before CP DMA."
D10.3.4.rst83 - radeonsi: Disable asynchronous DMA except for PIPE_BUFFER
D19.0.3.rst101 - radeonsi: use CP DMA for the null const buffer clear on CIK
D10.6.4.rst102 - radeonsi: completely rework updating descriptors without CP DMA
D18.1.5.rst146 - radv: make sure to wait for CP DMA when needed
D20.2.3.rst35 - iris: glClear with FBO imported from DMA-BUF doesn't work
D10.1.2.rst130 - r600g: disable async DMA on R700
D19.3.4.rst194 - svga: Fix banded DMA upload
/third_party/alsa-utils/alsaconf/po/
Dja.po46 " -R|--resources list available DMA and IRQ resources with debug for legacy\n"
65 " -R|--resources レガシーデバイスのデバッグ用: 可能な DMA と IRQ を表示する\n"
272 " Shall I try all possible DMA and IRQ combinations?\n"
277 " 可能な DMA と IRQ の全ての組合せを試みますか?\n"
Deu.po51 " -R|--resources list available DMA and IRQ resources with debug for "
77 " -R|--resources zerrendatu DMA eta IRQ baliabide eskuragarriak txartel "
290 " Shall I try all possible DMA and IRQ combinations?\n"
295 "DMA eta IRQ konbinazio guztiak probatzea nahi duzu?\n"
Dru.po50 " -R|--resources list available DMA and IRQ resources with debug for legacy\n"
282 " Shall I try all possible DMA and IRQ combinations?\n"
287 " Попробовать все доступные DMA и IRQ комбинации?\n"
/third_party/mesa3d/src/amd/common/
Dac_perfcounter.h79 DMA = 0x14, enumerator
/third_party/skia/third_party/externals/opengl-registry/extensions/NV/
DNV_vertex_array_range.txt47 Access (DMA). Unfortunately, the current OpenGL 1.1 vertex array
54 pass vertex indices to the hardware which can DMA the actual index's
89 enabled arrays is fair game. This makes it hard for a vertex DMA
96 are specified to be undefined. This permits hardware to DMA from
97 finite regions of OpenGL client address space, making DMA engine
106 have different DMA bandwidths and caching behavior, this extension
129 context DMA pointing to the old pages.
134 array range context DMA for the application's current address
DNV_pixel_data_range.txt47 prevented implementations from using DMA (Direct Memory Access)
62 model prevents asynchronous DMA transfers directly out of the user's
66 operations or on the size of the data. To facilitate DMA
75 Note that the types of memory that are suitable for DMA for reading
77 platforms, DMA pulling is best accomplished with write-combined
220 DMA extension for every single conceivable use in the future?
224 Maybe if the ARB wants to create a more generic "DMA" extension,
/third_party/openGLES/extensions/NV/
DNV_vertex_array_range.txt47 Access (DMA). Unfortunately, the current OpenGL 1.1 vertex array
54 pass vertex indices to the hardware which can DMA the actual index's
89 enabled arrays is fair game. This makes it hard for a vertex DMA
96 are specified to be undefined. This permits hardware to DMA from
97 finite regions of OpenGL client address space, making DMA engine
106 have different DMA bandwidths and caching behavior, this extension
129 context DMA pointing to the old pages.
134 array range context DMA for the application's current address
DNV_pixel_data_range.txt47 prevented implementations from using DMA (Direct Memory Access)
62 model prevents asynchronous DMA transfers directly out of the user's
66 operations or on the size of the data. To facilitate DMA
75 Note that the types of memory that are suitable for DMA for reading
77 platforms, DMA pulling is best accomplished with write-combined
220 DMA extension for every single conceivable use in the future?
224 Maybe if the ARB wants to create a more generic "DMA" extension,
/third_party/openGLES/extensions/SGIX/
DSGIX_depth_pass_instrument.txt69 order using a DMA. In this case the implementation will
72 application's buffer, we allow the DMA destination to be
/third_party/skia/third_party/externals/opengl-registry/extensions/SGIX/
DSGIX_depth_pass_instrument.txt69 order using a DMA. In this case the implementation will
72 application's buffer, we allow the DMA destination to be
/third_party/libdrm/man/
Ddrm.7.rst25 management, interrupt handling and DMA to provide a uniform interface to
/third_party/gstreamer/gstreamer/docs/random/ensonic/
Ddraft-bufferpools.txt107 - mlock: hardware that uses DMA needs buffers memory locked, if a buffer is

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