Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SILoadStoreOptimizer.cpp | 1612 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local 1623 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase() 1637 .addReg(DestSub1) in computeBase()
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D | SIInstrInfo.cpp | 5327 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local 5328 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp() 5334 .addReg(DestSub1) in splitScalar64BitUnaryOp() 5360 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitAddSub() local 5397 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub() 5407 .addReg(DestSub1) in splitScalar64BitAddSub() 5464 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local 5465 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() 5473 .addReg(DestSub1) in splitScalar64BitBinaryOp()
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D | SIISelLowering.cpp | 3617 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local 3640 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter() 3646 .addReg(DestSub1) in EmitInstrWithCustomInserter()
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