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/third_party/vixl/test/aarch32/
Dtest-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc367 const TestLoopData kTests[] = {{{F64, d3, d31, d11},
372 {{F64, d21, d17, d0},
377 {{F64, d8, d4, d16},
382 {{F64, d18, d11, d29},
387 {{F64, d18, d7, d16},
392 {{F64, d31, d28, d30},
397 {{F64, d3, d27, d4},
402 {{F64, d16, d17, d25},
407 {{F64, d12, d16, d21},
412 {{F64, d13, d3, d9},
[all …]
Dtest-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc367 const TestLoopData kTests[] = {{{F64, d3, d31, d11},
372 {{F64, d21, d17, d0},
377 {{F64, d8, d4, d16},
382 {{F64, d18, d11, d29},
387 {{F64, d18, d7, d16},
392 {{F64, d31, d28, d30},
397 {{F64, d3, d27, d4},
402 {{F64, d16, d17, d25},
407 {{F64, d12, d16, d21},
412 {{F64, d13, d3, d9},
[all …]
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-t32.cc97 {{{F64, d16, d17, d14}, false, al, "F64 d16 d17 d14", "F64_d16_d17_d14"},
98 {{F64, d21, d29, d16}, false, al, "F64 d21 d29 d16", "F64_d21_d29_d16"},
99 {{F64, d19, d28, d12}, false, al, "F64 d19 d28 d12", "F64_d19_d28_d12"},
101 {{F64, d31, d7, d1}, false, al, "F64 d31 d7 d1", "F64_d31_d7_d1"},
102 {{F64, d22, d6, d1}, false, al, "F64 d22 d6 d1", "F64_d22_d6_d1"},
106 {{F64, d29, d21, d18}, false, al, "F64 d29 d21 d18", "F64_d29_d21_d18"},
107 {{F64, d28, d29, d29}, false, al, "F64 d28 d29 d29", "F64_d28_d29_d29"},
108 {{F64, d26, d28, d26}, false, al, "F64 d26 d28 d26", "F64_d26_d28_d26"},
109 {{F64, d2, d18, d10}, false, al, "F64 d2 d18 d10", "F64_d2_d18_d10"},
110 {{F64, d4, d30, d6}, false, al, "F64 d4 d30 d6", "F64_d4_d30_d6"},
[all …]
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-a32.cc97 {{{F64, d16, d17, d14}, false, al, "F64 d16 d17 d14", "F64_d16_d17_d14"},
98 {{F64, d21, d29, d16}, false, al, "F64 d21 d29 d16", "F64_d21_d29_d16"},
99 {{F64, d19, d28, d12}, false, al, "F64 d19 d28 d12", "F64_d19_d28_d12"},
101 {{F64, d31, d7, d1}, false, al, "F64 d31 d7 d1", "F64_d31_d7_d1"},
102 {{F64, d22, d6, d1}, false, al, "F64 d22 d6 d1", "F64_d22_d6_d1"},
106 {{F64, d29, d21, d18}, false, al, "F64 d29 d21 d18", "F64_d29_d21_d18"},
107 {{F64, d28, d29, d29}, false, al, "F64 d28 d29 d29", "F64_d28_d29_d29"},
108 {{F64, d26, d28, d26}, false, al, "F64 d26 d28 d26", "F64_d26_d28_d26"},
109 {{F64, d2, d18, d10}, false, al, "F64 d2 d18 d10", "F64_d2_d18_d10"},
110 {{F64, d4, d30, d6}, false, al, "F64 d4 d30 d6", "F64_d4_d30_d6"},
[all …]
/third_party/vixl/examples/aarch32/
Dpi.cc58 __ Vdiv(F64, d6, d5, d0); in GenerateApproximatePi()
59 __ Vdiv(F64, d7, d5, d1); in GenerateApproximatePi()
60 __ Vdiv(F64, d8, d5, d2); in GenerateApproximatePi()
61 __ Vdiv(F64, d9, d5, d3); in GenerateApproximatePi()
63 __ Vadd(F64, d10, d10, d6); in GenerateApproximatePi()
64 __ Vadd(F64, d11, d11, d7); in GenerateApproximatePi()
65 __ Vadd(F64, d12, d12, d8); in GenerateApproximatePi()
66 __ Vadd(F64, d13, d13, d9); in GenerateApproximatePi()
68 __ Vadd(F64, d0, d0, d4); in GenerateApproximatePi()
69 __ Vadd(F64, d1, d1, d4); in GenerateApproximatePi()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td78 defm I32_TRUNC_S_SAT_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins),
79 [(set I32:$dst, (fp_to_sint F64:$src))],
83 defm I32_TRUNC_U_SAT_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins),
84 [(set I32:$dst, (fp_to_uint F64:$src))],
88 defm I64_TRUNC_S_SAT_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins),
89 [(set I64:$dst, (fp_to_sint F64:$src))],
93 defm I64_TRUNC_U_SAT_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins),
94 [(set I64:$dst, (fp_to_uint F64:$src))],
104 def : Pat<(int_wasm_trunc_saturate_signed F64:$src),
105 (I32_TRUNC_S_SAT_F64 F64:$src)>;
[all …]
DWebAssemblyInstrFloat.td20 defm _F64 : I<(outs F64:$dst), (ins F64:$src), (outs), (ins),
21 [(set F64:$dst, (node F64:$src))],
31 defm _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
32 [(set F64:$dst, (node F64:$lhs, F64:$rhs))],
41 defm _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
42 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
70 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
71 (COPYSIGN_F64 F64:$lhs, (F64_PROMOTE_F32 F32:$rhs))>;
72 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
73 (COPYSIGN_F32 F32:$lhs, (F32_DEMOTE_F64 F64:$rhs))>;
[all …]
DWebAssemblyRuntimeLibcallSignatures.cpp532 Params.push_back(wasm::ValType::F64); in getLibcallSignature()
547 Rets.push_back(wasm::ValType::F64); in getLibcallSignature()
551 Rets.push_back(wasm::ValType::F64); in getLibcallSignature()
552 Params.push_back(wasm::ValType::F64); in getLibcallSignature()
555 Rets.push_back(wasm::ValType::F64); in getLibcallSignature()
559 Rets.push_back(wasm::ValType::F64); in getLibcallSignature()
568 Params.push_back(wasm::ValType::F64); in getLibcallSignature()
580 Params.push_back(wasm::ValType::F64); in getLibcallSignature()
602 Rets.push_back(wasm::ValType::F64); in getLibcallSignature()
603 Params.push_back(wasm::ValType::F64); in getLibcallSignature()
[all …]
DWebAssemblyInstrInfo.td227 defm "": ARGUMENT<F64, f64>;
296 defm "" : LOCAL<F64>;
313 defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
315 [(set F64:$res, fpimm:$imm)],
/third_party/rust/crates/minimal-lexical/etc/correctness/test-parse-golang/parse-number-fxx-test-data/slowstrconv/
Dslowstrconv_test.go243 if got.F64 != wantF64 {
244 tt.Fatalf("tc=%q: F64: got 0x%08X, want 0x%08X", tc, got.F64, wantF64)
269 F64: 0x3FD5_5555_5555_5555,
Dslowstrconv.go49 F64 uint64 // 1 sign, 11 exponent (-1023 bias), 52 mantissa bits. member
71 r.F64 |= 0x8000_0000_0000_0000
90 F64: 0x0000_0000_0000_0000,
96 F64: 0x7FF0_0000_0000_0000,
123 ret.F64 = uint64(h.pack(exp2, 11, 52))
Dexample_test.go66 fmt.Printf("==== F64: 0x%016X\n", res.F64)
68 man := int64((res.F64 & 0x000F_FFFF_FFFF_FFFF) | 0x0010_0000_0000_0000)
69 exp := int(res.F64>>52) - 1023 - 52
/third_party/rust/crates/cxx/syntax/
Datom.rs20 F64, enumerator
46 "f64" => Some(F64), in from_str()
77 F64 => "f64", in as_ref()
Dpod.rs12 | Isize | F32 | F64 => true, in is_guaranteed_pod()
/third_party/vixl/test/aarch32/config/
Dcond-dt-drt-drd-drn-drm-float.json32 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; A2
34 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; T2
56 // VSUB{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; A2
58 // VSUB{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; T2
/third_party/vixl/src/aarch32/
Doperands-aarch32.h257 : imm_(immediate), immediate_type_(F64) {} in NeonImmediate()
273 if (immediate_type_.Is(F64) || immediate_type_.Is(F32)) return 0; in GetImmediate()
280 if (immediate_type_.Is(F64) || immediate_type_.Is(F32)) return 0; in GetImmediate()
285 if (immediate_type_.Is(F64)) return static_cast<float>(imm_.d_); in GetImmediate()
298 bool IsDouble() const { return immediate_type_.Is(F64); } in IsDouble()
301 if (immediate_type_.Is(F64)) return imm_.d_ == 0.0; in IsFloatZero()
316 (immediate_type_.Is(F64) && (imm_.d_ == 0.0)); in CanConvert()
322 (immediate_type_.Is(F64) && (imm_.d_ == 0.0)); in CanConvert()
/third_party/gstreamer/gstplugins_good/tests/check/elements/
Daudioecho.c37 "format = (string) " GST_AUDIO_NE(F64)
46 GST_AUDIO_NE (F32) ", " GST_AUDIO_NE (F64) " }"));
54 GST_AUDIO_NE (F32) ", " GST_AUDIO_NE (F64) " }"));
Dequalizer.c37 "format = (string) "GST_AUDIO_NE (F64) ", " \
46 "format = (string) " GST_AUDIO_NE (F64) ", "
54 "format = (string) " GST_AUDIO_NE (F64) ", "
/third_party/openGLES/extensions/NV/
DNV_shader_atomic_float64.txt125 specified in an assembly program, "F64" should be allowed as a storage
135 "F64" storage modifier with the "ATOM" opcode to perform atomic double-
143 ADD U32, S32, U64, F32, F64 compute a sum
146 EXCH U32, S32, U64, F32, F64 exchange memory with operand
/third_party/skia/third_party/externals/opengl-registry/extensions/NV/
DNV_shader_atomic_float64.txt125 specified in an assembly program, "F64" should be allowed as a storage
135 "F64" storage modifier with the "ATOM" opcode to perform atomic double-
143 ADD U32, S32, U64, F32, F64 compute a sum
146 EXCH U32, S32, U64, F32, F64 exchange memory with operand
/third_party/node/deps/v8/src/wasm/
Dwasm-opcodes-inl.h30 #define CASE_F64_OP(name, str) CASE_OP(F64##name, "f64." str)
131 CASE_CONVERT_OP(Convert, INT, F64, "f64", "trunc") in OpcodeName()
136 CASE_CONVERT_OP(Convert, F64, I32, "i32", "convert") in OpcodeName()
137 CASE_CONVERT_OP(Convert, F64, I64, "i64", "convert") in OpcodeName()
230 CASE_CONVERT_SAT_OP(Convert, I32, F64, "f64", "trunc") in OpcodeName()
232 CASE_CONVERT_SAT_OP(Convert, I64, F64, "f64", "trunc") in OpcodeName()
Dvalue-type.h39 V(F64, 3, F64, Float64, 'd', "f64") \
644 V(F64, , Float64) \
720 V(F64, , Float64) \
/third_party/gstreamer/gstplugins_base/tests/check/elements/
Daudioresample.c837 test_pipeline (GST_AUDIO_NE (F64), 44100, 48000, quality); in GST_START_TEST()
838 test_pipeline (GST_AUDIO_NE (F64), 48000, 44100, quality); in GST_START_TEST()
1014 caps = gst_caps_from_string ("audio/x-raw, format=" GST_AUDIO_NE (F64) in GST_START_TEST()
1029 caps = gst_caps_from_string ("audio/x-raw, format=" GST_AUDIO_NE (F64) in GST_START_TEST()
1146 FFT_HELPERS (double, F64, f64, 2048.0);
1239 GST_AUDIO_NE (F64), &init_double_silence, &compare_ffts_F64); in GST_START_TEST()
1241 GST_AUDIO_NE (F64), &init_double_sine, &compare_ffts_F64); in GST_START_TEST()
1243 GST_AUDIO_NE (F64), &init_double_sine2, &compare_ffts_F64); in GST_START_TEST()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td409 def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>;
422 def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>;
424 def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>;
427 def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>;
429 def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>;
434 def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
435 def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
649 def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>;
650 def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>;
651 def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>;
[all …]
/third_party/vixl/tools/test_generator/
Ddata_types.py363 class F64(Scalar): class
398 class DRegisterF64(F64):

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