Searched refs:FLD (Results 1 – 14 of 14) sorted by relevance
| /third_party/pcre2/pcre2/src/ |
| D | pcre2test.c | 1086 #define FLD(a,b) ((test_mode == PCRE8_MODE)? G(a,8)->b : \ macro
1635 #define FLD(a,b) \ macro
2054 #define FLD(a,b) G(a,8)->b macro
2162 #define FLD(a,b) G(a,16)->b macro
2270 #define FLD(a,b) G(a,32)->b macro
4087 8 * (FLD(compiled_code, flags) & PCRE2_MODE_MASK)); in pattern_info()
4404 BOOL utf = (FLD(compiled_code, overall_options) & PCRE2_UTF) != 0; in callout_callback()
4452 BOOL utf = (FLD(compiled_code, overall_options) & PCRE2_UTF) != 0; in show_pattern_info()
4673 (FLD(compiled_code, flags) & PCRE2_BSR_SET) != 0) in show_pattern_info()
4677 if ((FLD(compiled_code, flags) & PCRE2_NL_SET) != 0) in show_pattern_info()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 72 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
204 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
312 defm : LdPat<load, FLD>;
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| D | RISCVMergeBaseOffset.cpp | 220 case RISCV::FLD: in detectAndFoldOffset()
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| D | RISCVISelDAGToDAG.cpp | 227 case RISCV::FLD: in doPeepholeLoadStoreADDI()
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| D | RISCVInstrInfo.cpp | 52 case RISCV::FLD: in isLoadFromStackSlot()
157 Opcode = RISCV::FLD; in loadRegFromStackSlot()
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| D | RISCVInstrInfoC.td | 759 def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
871 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeRISCV_common.c | 97 #define FLD (F3(0x3) | OPC(0x7)) macro
762 FAIL_IF(push_inst(compiler, FLD | FRD(i) | RS1(SLJIT_SP) | IMM_I(offset))); in emit_stack_frame_release()
767 FAIL_IF(push_inst(compiler, FLD | FRD(i) | RS1(SLJIT_SP) | IMM_I(offset))); in emit_stack_frame_release()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 677 FLD, enumerator
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| D | X86InstrFPStack.td | 29 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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| D | X86SchedHaswell.td | 732 // FLD.
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| D | X86ISelDAGToDAG.cpp | 1146 Result = CurDAG->getMemIntrinsicNode(X86ISD::FLD, dl, VTs, Ops, MemVT, in PreprocessISelDAG()
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| D | X86ISelLowering.cpp | 19547 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, TheVT, MMO); in FP_TO_INTHelper()
29612 case X86ISD::FLD: return "X86ISD::FLD"; in getTargetNodeName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 1858 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
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| /third_party/astc-encoder/Test/Images/HDRIHaven/HDR-RGB/ |
| D | hdr-rgb-riverwalk.hdr | 7649 <FLD=3^9oX�ƭyliz V�}~}}|{{|�}�~�}|}{}}|}}}z{|}}|{|{�|�}�|}|}|||}�~+}}}|||{|~~}|}}}{||}~~}{|||{||…
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