Searched refs:FPRoundOdd (Results 1 – 6 of 6) sorted by relevance
| /third_party/vixl/src/ |
| D | utils-vixl.h | 1227 FPRoundOdd
1255 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd));
1334 VIXL_ASSERT(round_mode == FPRoundOdd);
1367 VIXL_ASSERT(round_mode == FPRoundOdd);
1411 VIXL_ASSERT(round_mode == FPRoundOdd);
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| D | utils-vixl.cc | 340 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPToFloat()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | instructions-arm64.h | 76 FPRoundOdd enumerator
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-arm64.h | 58 DCHECK((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPRound()
137 DCHECK_EQ(round_mode, FPRoundOdd); in FPRound()
170 DCHECK_EQ(round_mode, FPRoundOdd); in FPRound()
210 DCHECK_EQ(round_mode, FPRoundOdd); in FPRound()
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| D | simulator-logic-arm64.cc | 294 DCHECK((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPToFloat()
3864 dst.SetFloat(i, FPToFloat(src.Float<double>(i), FPRoundOdd)); in fcvtxn()
3874 dst.SetFloat(i + lane_count, FPToFloat(src.Float<double>(i), FPRoundOdd)); in fcvtxn2()
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| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 6049 dst.SetFloat(i, FPToFloat(srctmp.Float<double>(i), FPRoundOdd, ReadDN())); in fcvtxn()
6062 FPToFloat(src.Float<double>(i), FPRoundOdd, ReadDN())); in fcvtxn2()
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