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Searched refs:FPTieEven (Results 1 – 10 of 10) sorted by relevance

/third_party/vixl/src/
Dutils-vixl.cc210 Float16ToRawbits(FPToFloat16(dvalue, FPTieEven, kIgnoreDefaultNaN)); in Float16()
340 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPToFloat()
452 VIXL_ASSERT(round_mode == FPTieEven); in FPToFloat16()
507 VIXL_ASSERT(round_mode == FPTieEven); in FPToFloat16()
Dutils-vixl.h1219 FPTieEven = 0x0,
1255 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd));
1329 if (round_mode == FPTieEven) {
1363 if (round_mode == FPTieEven) {
1388 if (round_mode == FPTieEven) {
1510 return FPToFloat16(value, FPTieEven, kIgnoreDefaultNaN);
1515 return FPToFloat16(value, FPTieEven, kIgnoreDefaultNaN);
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-arm64.cc2911 set_wreg(dst, FPToInt32(sreg(src), FPTieEven)); in VisitFPIntegerConvert()
2914 set_xreg(dst, FPToInt64(sreg(src), FPTieEven)); in VisitFPIntegerConvert()
2917 set_wreg(dst, FPToInt32(dreg(src), FPTieEven)); in VisitFPIntegerConvert()
2920 set_xreg(dst, FPToInt64(dreg(src), FPTieEven)); in VisitFPIntegerConvert()
2923 set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); in VisitFPIntegerConvert()
2926 set_xreg(dst, FPToUInt64(sreg(src), FPTieEven)); in VisitFPIntegerConvert()
2929 set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); in VisitFPIntegerConvert()
2932 set_xreg(dst, FPToUInt64(dreg(src), FPTieEven)); in VisitFPIntegerConvert()
3156 set_sreg(fd, FPToFloat(dreg(fn), FPTieEven)); in VisitFPDataProcessing1Source()
3159 set_hreg(fd, FPToFloat16(sreg(fn), FPTieEven)); in VisitFPDataProcessing1Source()
[all …]
Dsimulator-arm64.h58 DCHECK((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPRound()
132 if (round_mode == FPTieEven) { in FPRound()
166 if (round_mode == FPTieEven) { in FPRound()
187 if (round_mode == FPTieEven) { in FPRound()
2303 DCHECK(fpcr().RMode() == FPTieEven); // Ties-to-even rounding only. in AssertSupportedFPCR()
Dsimulator-logic-arm64.cc198 DCHECK_EQ(round_mode, FPTieEven); in FPToFloat16()
246 DCHECK_EQ(round_mode, FPTieEven); in FPToFloat16()
294 DCHECK((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPToFloat()
3176 case FPTieEven: { in FPRoundInt()
3831 dst.SetFloat(i, FPToFloat16(src.Float<float>(i), FPTieEven)); in fcvtn()
3836 dst.SetFloat(i, FPToFloat(src.Float<double>(i), FPTieEven)); in fcvtn()
3848 dst.SetFloat(i + lane_count, FPToFloat16(src.Float<float>(i), FPTieEven)); in fcvtn2()
3853 dst.SetFloat(i + lane_count, FPToFloat(src.Float<double>(i), FPTieEven)); in fcvtn2()
4009 case FPTieEven: in FPRecipEstimate()
/third_party/vixl/src/aarch64/
Dsimulator-aarch64.cc5689 WriteWRegister(dst, FPToInt32(ReadHRegister(src), FPTieEven)); in Simulator()
5692 WriteXRegister(dst, FPToInt64(ReadHRegister(src), FPTieEven)); in Simulator()
5695 WriteWRegister(dst, FPToInt32(ReadSRegister(src), FPTieEven)); in Simulator()
5698 WriteXRegister(dst, FPToInt64(ReadSRegister(src), FPTieEven)); in Simulator()
5701 WriteWRegister(dst, FPToInt32(ReadDRegister(src), FPTieEven)); in Simulator()
5704 WriteXRegister(dst, FPToInt64(ReadDRegister(src), FPTieEven)); in Simulator()
5707 WriteWRegister(dst, FPToUInt32(ReadHRegister(src), FPTieEven)); in Simulator()
5710 WriteXRegister(dst, FPToUInt64(ReadHRegister(src), FPTieEven)); in Simulator()
5713 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPTieEven)); in Simulator()
5716 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPTieEven)); in Simulator()
[all …]
Dlogic-aarch64.cc4808 case FPTieEven: { in FPRoundIntCommon()
6000 FPTieEven, in fcvtn()
6006 dst.SetFloat(i, FPToFloat(srctmp.Float<double>(i), FPTieEven, ReadDN())); in fcvtn()
6021 FPToFloat16(src.Float<float>(i), FPTieEven, ReadDN()))); in fcvtn2()
6027 FPToFloat(src.Float<double>(i), FPTieEven, ReadDN())); in fcvtn2()
6213 case FPTieEven: in FPRecipEstimate()
Dsimulator-aarch64.h4724 VIXL_ASSERT(ReadFpcr().GetRMode() == FPTieEven);
/third_party/node/deps/v8/src/codegen/arm64/
Dinstructions-arm64.h68 FPTieEven = 0x0, enumerator
Dmacro-assembler-arm64.cc1451 STATIC_ASSERT(FPTieEven == 0); in AssertFPCRState()