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Searched refs:FREG (Results 1 – 3 of 3) sorted by relevance

/third_party/libunwind/src/riscv/
Dsetcontext.S29 #define FREG(X) (UC_MCONTEXT_REGS_OFF + SZREG * 32 + SZFREG * X)(a0) macro
39 lw a1, FREG(32)
42 LOAD_FP fs0, FREG(8)
43 LOAD_FP fs1, FREG(9)
44 LOAD_FP fs2, FREG(18)
45 LOAD_FP fs3, FREG(19)
46 LOAD_FP fs4, FREG(20)
47 LOAD_FP fs5, FREG(21)
48 LOAD_FP fs6, FREG(22)
49 LOAD_FP fs7, FREG(23)
[all …]
Dgetcontext.S29 #define FREG(X) (UC_MCONTEXT_REGS_OFF + SZREG * 32 + SZFREG * X)(a0) macro
64 sw a1, FREG(32)
66 STORE_FP fs0, FREG(8)
67 STORE_FP fs1, FREG(9)
68 STORE_FP fs2, FREG(18)
69 STORE_FP fs3, FREG(19)
70 STORE_FP fs4, FREG(20)
71 STORE_FP fs5, FREG(21)
72 STORE_FP fs6, FREG(22)
73 STORE_FP fs7, FREG(23)
[all …]
/third_party/elfutils/libcpu/
Driscv_disasm.c91 #define FREG(nr) ((char *) fregnames[nr]) macro
92 #define FREGP(nr) FREG (8 + (nr))
267 op[0] = FREG ((first >> 7) & 0x1f); in riscv_disasm()
352 op[0] = FREG ((first >> 7) & 0x1f); in riscv_disasm()
470 op[0] = FREG ((first >> 2) & 0x1f); in riscv_disasm()
516 op[0] = FREG ((first & 0x7c) >> 2); in riscv_disasm()
558 op[0] = idx == 0x00 ? REG (rd) : FREG (rd); in riscv_disasm()
683 op[0] = idx == 0x08 ? REG (rs2) : FREG (rs2); in riscv_disasm()
806 op[0] = FREG (rd); in riscv_disasm()
807 op[1] = FREG (rs1); in riscv_disasm()
[all …]