Searched refs:Haswell (Results 1 – 25 of 34) sorted by relevance
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40 const uint32_t Haswell[] = { variable105 return std::find(std::begin(Haswell), std::end(Haswell), DeviceId) != std::end(Haswell); in IsHaswell()
2 asound.state.Haswell \
187 - i965: Update URB partitioning code for Haswell's GT3 variant.188 - i965: Add chipset limits for the Haswell GT3 variant.194 - i965: Use the correct restart index for fixed index mode on Haswell.256 - i965: Add missing Haswell GT3 Desktop to IS_HSW_GT3 check.257 - i965: Adding more reserved PCI IDs for Haswell.
171 - i965: Fix primitive restart on Haswell.173 - i965: Do texture swizzling in hardware on Haswell.175 - i965: Use Haswell's sample_d_c for textureGrad with shadow samplers.176 - i965: Add chipset limits for Haswell GT1/GT2.
72 - i965: Fix Line Stipple enable bit in 3DSTATE_SF for Haswell.
69 - i965: Fix integer border color on Haswell.
55 - i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround
108 - i965: Fall back to GL 4.2/4.3 on Haswell if the kernel isn't new
75 [i965 on HD4600 Haswell] xcom switch to ingame cinematics cause259 - anv: Properly call gen75_emit_state_base_address on Haswell.
161 - i965: Fix INTEL_DEBUG=shader_time for Haswell.
32 - [i965] Downward causes GPU hangs and misrendering on Haswell
163 - i965/vs: Fix textureGrad() with shadow samplers on Haswell.
241 379b24a40d3d34ffdaaeb1b328f50e28ecb01468 on Haswell
36 - Intel Haswell now supports OpenGL 4.2
213 [i965 on HD4600 Haswell] xcom switch to ingame cinematics cause
156 379b24a40d3d34ffdaaeb1b328f50e28ecb01468 on Haswell
283 case on Haswell
2374 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.2540 ; Unroll for better performance on Haswell.2553 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.2568 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.2743 ; Unroll for better performance on Haswell.2765 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.2781 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.2993 ; Unroll for better performance on Haswell.3006 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.3022 ; Increment addresses for the next iteration. Doing this early is beneficial on Haswell.[all …]
82 …Haswell X :math:`u_6` :math:`u_5` :math:`v_3 \oplus u_1` :math:`v_7` :math:`v_6` :math:…83 …Haswell Y :math:`u_6` :math:`u_5` :math:`v_2 \oplus u_1` :math:`v_7` :math:`v_6` :math:…
67 The best documentation for bit-6 swizzling can be found in the Haswell PRM Vol.
28 Haswell, Cherryview).
1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//9 // This file defines the machine model for Haswell to support instruction37 // Haswell can issue micro-ops to 8 different ports in one cycle.1863 // section "Haswell and Broadwell Pipeline" > "Register allocation and
373 // Gather is available since Haswell (AVX2 set). So technically, we can568 // Haswell
1610 // section "Haswell and Broadwell Pipeline" > "Register allocation and
213 …itecture when using hyper-threading. Newer microarchitectures, including Haswell, are unaffected. …