| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 810 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
818 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
826 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
850 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
861 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
878 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| D | HexagonPatterns.td | 124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
506 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
509 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
525 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
830 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
840 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1022 (A2_swiz (HiReg $Rss)))>;
1060 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>;
1062 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>;
1330 (Combinew (S2_clrbit_i (HiReg $Rs), 31),
[all …]
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| D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| D | HexagonFrameLowering.cpp | 976 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
978 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.h | 52 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
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| D | AVRRegisterInfo.cpp | 269 unsigned &HiReg) const { in splitReg()
273 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 187 unsigned HiReg = 0; member
1598 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1625 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
1728 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
1774 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
1832 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| D | AMDGPUInstructionSelector.cpp | 1465 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
1470 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
1476 .addReg(HiReg) in selectG_CONSTANT()
1674 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
1680 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_PTR_MASK()
1689 .addReg(HiReg) in selectG_PTR_MASK()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| D | MipsSEInstrInfo.cpp | 814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
862 .addReg(HiReg); in expandBuildPairF64()
867 .addReg(HiReg); in expandBuildPairF64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 4790 unsigned SrcReg, LoReg, HiReg; in Select() local
4795 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
4799 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
4847 assert(HiReg && "Register for high half is not defined!"); in Select()
4848 SDValue ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, in Select()
4885 unsigned LoReg, HiReg, ClrReg; in Select() local
4890 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
4894 LoReg = X86::AX; HiReg = X86::DX; in Select()
4899 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
4903 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1136 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
1140 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
1151 .addReg(HiReg) in emitReadCycleWidePseudo()
1172 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
1186 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
1205 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
1218 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 7177 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7185 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 11342 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
11344 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
11351 .addReg(HiReg) in EmitInstrWithCustomInserter()
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