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Searched refs:I915_ENGINE_CLASS_RENDER (Results 1 – 18 of 18) sorted by relevance

/third_party/mesa3d/src/intel/common/
Dintel_gem.c91 [I915_ENGINE_CLASS_RENDER] = -1, in intel_gem_create_context_engines()
97 [I915_ENGINE_CLASS_RENDER] = in intel_gem_create_context_engines()
98 intel_gem_count_engines(info, I915_ENGINE_CLASS_RENDER), in intel_gem_create_context_engines()
110 assert(engine_class == I915_ENGINE_CLASS_RENDER || in intel_gem_create_context_engines()
Dintel_decoder.c169 group->engine_mask = I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER) | in create_group()
189 group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER); in create_group()
Dintel_batch_decoder.c54 ctx->engine = I915_ENGINE_CLASS_RENDER; in intel_batch_decode_ctx_init()
/third_party/mesa3d/src/intel/tools/
Daub_read.c151 enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER; in handle_trace_block()
166 engine = I915_ENGINE_CLASS_RENDER; in handle_trace_block()
207 engine = I915_ENGINE_CLASS_RENDER; in handle_memtrace_reg_write()
250 engine = I915_ENGINE_CLASS_RENDER; in handle_memtrace_reg_write()
Daubinator_error_decode.c85 { I915_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
93 { I915_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
100 { I915_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
108 [I915_ENGINE_CLASS_RENDER] = "rcs", in ring_name_to_class()
126 { "render", I915_ENGINE_CLASS_RENDER, 0 }, in ring_name_to_class()
175 case I915_ENGINE_CLASS_RENDER: in instdone_register_for_ring()
Daub_write.c358 [I915_ENGINE_CLASS_RENDER] = {
360 .engine_class = I915_ENGINE_CLASS_RENDER,
454 case I915_ENGINE_CLASS_RENDER: in engine_from_engine_class()
471 [I915_ENGINE_CLASS_RENDER] = gfx8_render_context_init, in get_context_init()
476 [I915_ENGINE_CLASS_RENDER] = gfx10_render_context_init, in get_context_init()
507 case I915_ENGINE_CLASS_RENDER: reg = RCSUNIT (HWS_PGA); break; in write_hwsp()
782 [I915_ENGINE_CLASS_RENDER] = AUB_TRACE_TYPE_RING_PRB0, in aub_dump_ring_buffer_legacy()
Derror2aub.c200 { "rcs", I915_ENGINE_CLASS_RENDER, true }, in engine_from_name()
205 { "render command stream", I915_ENGINE_CLASS_RENDER, false }, in engine_from_name()
534 aub_write_exec(&aub, 0, batch_bo->addr, 0, I915_ENGINE_CLASS_RENDER); in main()
Dintel_noop_drm_shim.c369 I915_ENGINE_CLASS_RENDER; in i915_ioctl_query()
Dintel_dump_gpu.c195 return I915_ENGINE_CLASS_RENDER; in engine_class_from_ring_flag()
Daubinator_viewer_decoder.cpp46 ctx->engine = I915_ENGINE_CLASS_RENDER; in aub_viewer_decode_ctx_init()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_batch.c281 if (intel_gem_count_engines(engines_info, I915_ENGINE_CLASS_RENDER) < 1) { in iris_create_engines_context()
288 [IRIS_BATCH_RENDER] = I915_ENGINE_CLASS_RENDER, in iris_create_engines_context()
289 [IRIS_BATCH_COMPUTE] = I915_ENGINE_CLASS_RENDER, in iris_create_engines_context()
/third_party/mesa3d/src/intel/vulkan/
Danv_utrace.c270 case I915_ENGINE_CLASS_RENDER: in queue_family_to_name()
Danv_perf.c356 if (queue_family->engine_class != I915_ENGINE_CLASS_RENDER) in anv_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR()
Danv_device.c679 I915_ENGINE_CLASS_RENDER); in anv_physical_device_init_queue_families()
686 c_count < 1 ? I915_ENGINE_CLASS_RENDER : I915_ENGINE_CLASS_COMPUTE; in anv_physical_device_init_queue_families()
696 .engine_class = I915_ENGINE_CLASS_RENDER, in anv_physical_device_init_queue_families()
704 .engine_class = I915_ENGINE_CLASS_RENDER, in anv_physical_device_init_queue_families()
726 .engine_class = I915_ENGINE_CLASS_RENDER, in anv_physical_device_init_queue_families()
DgenX_state.c468 case I915_ENGINE_CLASS_RENDER: in genX()
/third_party/mesa3d/src/intel/ds/
Dintel_driver_ds.cc146 case I915_ENGINE_CLASS_RENDER: in i915_engine_class_to_category()
/third_party/libdrm/include/drm/
Di915_drm.h119 I915_ENGINE_CLASS_RENDER = 0, enumerator
/third_party/mesa3d/include/drm-uapi/
Di915_drm.h176 I915_ENGINE_CLASS_RENDER = 0, enumerator