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Searched refs:ISL_AUX_USAGE_HIZ_CCS_WT (Results 1 – 12 of 12) sorted by relevance

/third_party/mesa3d/src/intel/isl/
Disl_surface_state.c76 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
227 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_genX()
532 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_genX()
Disl_emit_depth_stencil.c268 info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT; in isl_genX()
Disl.h817 ISL_AUX_USAGE_HIZ_CCS_WT, enumerator
2150 usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_aux_usage_has_hiz()
2168 usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_aux_usage_has_ccs()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_resolve.c526 case ISL_AUX_USAGE_HIZ_CCS_WT: in iris_sample_with_depth_aux()
891 case ISL_AUX_USAGE_HIZ_CCS_WT: in iris_resource_texture_aux_usage()
1067 case ISL_AUX_USAGE_HIZ_CCS_WT: in iris_resource_render_aux_usage()
Diris_blit.c580 case ISL_AUX_USAGE_HIZ_CCS_WT: in get_copy_region_aux_settings()
Diris_clear.c473 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) { in fast_clear_depth()
Diris_resource.c818 res->aux.usage = ISL_AUX_USAGE_HIZ_CCS_WT; in iris_resource_configure_aux()
843 case ISL_AUX_USAGE_HIZ_CCS_WT: in iris_resource_configure_aux()
/third_party/mesa3d/src/intel/vulkan/
Danv_image.c775 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ_CCS_WT; in add_aux_surface_if_supported()
787 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) in add_aux_surface_if_supported()
1982 image->planes[p].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT); in anv_BindImageMemory2()
2213 case ISL_AUX_USAGE_HIZ_CCS_WT: in anv_layout_to_aux_state()
2238 case ISL_AUX_USAGE_HIZ_CCS_WT: in anv_layout_to_aux_state()
Danv_blorp.c1753 depth.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) { in anv_image_hiz_clear()
/third_party/mesa3d/src/intel/blorp/
Dblorp_clear.c928 } else if (aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) { in blorp_can_hiz_clear_depth()
Dblorp_blit.c2910 params.src.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in blorp_copy()
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst2380 - intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT
2382 - iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZ
2383 - intel/isl: Require ISL_AUX_USAGE_HIZ_CCS_WT for HZ+CCS WT mode