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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
47 field bits<16> Inst;
61 bits<16> Inst;
63 let Inst{15-10} = 0x01;
64 let Inst{9-7} = rd;
65 let Inst{6-4} = rt;
66 let Inst{3-1} = rs;
67 let Inst{0} = funct;
75 bits<16> Inst;
77 let Inst{15-10} = funct;
[all …]
DMicroMips32r6InstrFormats.td40 bits<16> Inst;
42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
50 bits<16> Inst;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
60 bits<16> Inst;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
[all …]
DMipsInstrFormats.td74 field bits<32> Inst;
84 let Inst{31-26} = Opcode;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
184 let Inst{25-21} = rs;
185 let Inst{20-16} = rt;
186 let Inst{15-0} = imm16;
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DMipsMSAInstrFormats.td12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
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DMicroMipsDSPInstrFormats.td29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
40 let Inst{31-26} = 0b000000;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
44 let Inst{5-0} = 0b111100;
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DMips32r6InstrFormats.td181 bits<32> Inst;
183 let Inst{31-26} = OPGROUP_AUI.Value;
184 let Inst{25-21} = rs;
185 let Inst{20-16} = rt;
186 let Inst{15-0} = imm;
190 let Inst{31-26} = OPGROUP_DAUI.Value;
196 bits<32> Inst;
198 let Inst{31-26} = OPGROUP_REGIMM.Value;
199 let Inst{25-21} = 0b00000;
200 let Inst{20-16} = OPCODE5_BGEZAL.Value;
[all …]
DMipsDSPInstrFormats.td72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
76 let Inst{5-0} = 0b010000;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
88 let Inst{10-6} = op;
89 let Inst{5-0} = 0b010000;
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DMipsMTInstrFormats.td40 bits<32> Inst;
43 let Inst{31-26} = 0b010000; // COP0
44 let Inst{25-21} = 0b01011; // MFMC0
45 let Inst{20-16} = rt;
46 let Inst{15-11} = Op1.Value;
47 let Inst{10-6} = Op2.Value;
48 let Inst{5} = sc.Value;
49 let Inst{4-3} = 0b00;
50 let Inst{2-0} = 0b001;
54 bits<32> Inst;
[all …]
DMips16InstrFormats.td58 field bits<16> Inst;
62 let Inst{15-11} = Opcode;
75 field bits<32> Inst;
85 let Inst{31-27} = 0b11110;
110 let Inst{10-0} = imm11;
126 let Inst{10-8} = rx;
127 let Inst{7-0} = imm8;
145 let Inst{10-8} = rx;
146 let Inst{7-5} = ry;
147 let Inst{4-0} = funct;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrFormats.td13 let Inst{20-16} = Rs32{4-0};
15 let Inst{4-0} = Rd32{4-0};
17 let Inst{6-5} = Pe4{1-0};
21 let Inst{6-5} = Qs4{1-0};
23 let Inst{20-16} = Rt32{4-0};
25 let Inst{13-13} = Mu2{0-0};
27 let Inst{12-8} = Vv32{4-0};
29 let Inst{4-0} = Vw32{4-0};
33 let Inst{17-16} = Ps4{1-0};
35 let Inst{9-8} = Pt4{1-0};
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DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
17 let Inst{31-21} = 0b10001100100;
27 let Inst{13-5} = 0b000000110;
28 let Inst{31-21} = 0b10000000100;
36 let Inst{13-5} = 0b000000101;
37 let Inst{31-21} = 0b10001100100;
48 let Inst{7-5} = 0b000;
49 let Inst{13-13} = 0b0;
50 let Inst{31-21} = 0b11110011000;
64 let Inst{7-5} = 0b011;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
92 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
95 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); in DecodeGR32BitRegisterClass()
98 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGRH32BitRegisterClass() argument
101 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); in DecodeGRH32BitRegisterClass()
104 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
107 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); in DecodeGR64BitRegisterClass()
110 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR128BitRegisterClass() argument
113 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); in DecodeGR128BitRegisterClass()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td15 field bits<32> Inst;
22 let Inst{0-5} = opcode;
76 field bits<64> Inst;
83 let Inst{0-5} = opcode1;
84 let Inst{32-37} = opcode2;
119 let Inst{6-29} = LI;
120 let Inst{30} = aa;
121 let Inst{31} = lk;
135 let Inst{6-10} = BIBO{4-0};
136 let Inst{11-15} = BI;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp63 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, in DecodePCRel24BranchTarget() argument
67 Inst.addOperand(MCOperand::createImm(Offset)); in DecodePCRel24BranchTarget()
75 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
82 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRRCRegisterClass() argument
85 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
88 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRBITRCRegisterClass() argument
91 return decodeRegisterClass(Inst, RegNo, CRBITRegs); in DecodeCRBITRCRegisterClass()
94 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeF4RCRegisterClass() argument
97 return decodeRegisterClass(Inst, RegNo, FRegs); in DecodeF4RCRegisterClass()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
185 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
188 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
191 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
195 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
198 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp59 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGPRRegisterClass() argument
72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
76 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR32RegisterClass() argument
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
87 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR32CRegisterClass() argument
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
98 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR64RegisterClass() argument
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
109 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR64CRegisterClass() argument
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCInstrFormats.td14 field bits<64> Inst;
145 // A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
160 let Inst{31-27} = major;
161 let Inst{16} = b16;
162 let Inst{5} = N;
170 let Inst{26-18} = S21{10-2};
171 let Inst{15-6} = S21{20-11};
172 let Inst{4-0} = cc;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td30 field bits<16> Inst;
39 field bits<32> Inst;
75 let Inst{15-12} = opcode;
76 let Inst{11-10} = f;
77 let Inst{9} = rr{4};
78 let Inst{8-4} = rd;
79 let Inst{3-0} = rr{3-0};
87 let Inst{15-12} = opcode;
88 let Inst{11-10} = f;
89 let Inst{9} = rd{4};
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DEarlyCSE.cpp97 Instruction *Inst; member
99 SimpleValue(Instruction *I) : Inst(I) { in SimpleValue()
104 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() || in isSentinel()
105 Inst == DenseMapInfo<Instruction *>::getTombstoneKey(); in isSentinel()
108 static bool canHandle(Instruction *Inst) { in canHandle()
110 if (CallInst *CI = dyn_cast<CallInst>(Inst)) in canHandle()
112 return isa<CastInst>(Inst) || isa<UnaryOperator>(Inst) || in canHandle()
113 isa<BinaryOperator>(Inst) || isa<GetElementPtrInst>(Inst) || in canHandle()
114 isa<CmpInst>(Inst) || isa<SelectInst>(Inst) || in canHandle()
115 isa<ExtractElementInst>(Inst) || isa<InsertElementInst>(Inst) || in canHandle()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
102 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
107 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
112 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
117 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
122 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
127 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DCFLGraph.h263 void visitReturnInst(ReturnInst &Inst) { in visitReturnInst() argument
264 if (auto RetVal = Inst.getReturnValue()) { in visitReturnInst()
272 void visitPtrToIntInst(PtrToIntInst &Inst) { in visitPtrToIntInst() argument
273 auto *Ptr = Inst.getOperand(0); in visitPtrToIntInst()
277 void visitIntToPtrInst(IntToPtrInst &Inst) { in visitIntToPtrInst() argument
278 auto *Ptr = &Inst; in visitIntToPtrInst()
282 void visitCastInst(CastInst &Inst) { in visitCastInst() argument
283 auto *Src = Inst.getOperand(0); in visitCastInst()
284 addAssignEdge(Src, &Inst); in visitCastInst()
287 void visitBinaryOperator(BinaryOperator &Inst) { in visitBinaryOperator() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrFormatsC.td16 field bits<16> Inst;
42 let Inst{15-12} = funct4;
43 let Inst{11-7} = rs1;
44 let Inst{6-2} = rs2;
45 let Inst{1-0} = opcode;
49 // is responsible for setting the appropriate bits in the Inst field.
50 // The bits Inst{6-2} must be set for each instruction.
58 let Inst{15-13} = funct3;
59 let Inst{12} = imm{5};
60 let Inst{11-7} = rd;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrFormats.td431 field bits<32> Inst;
434 // target encoding differs from its value in the "Inst" field,
552 let Inst{31-28} = p;
584 let Inst{31-28} = p;
585 let Inst{20} = s;
632 let Inst{27-24} = opcod;
638 let Inst{27-24} = opcod;
653 let Inst{27-23} = 0b00011;
654 let Inst{22-21} = opcod;
655 let Inst{20} = 1;
[all …]

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