Searched refs:IsX (Results 1 – 12 of 12) sorted by relevance
| /third_party/vixl/src/aarch64/ |
| D | operands-aarch64.h | 600 return base_.IsX() && regoffset_.IsNone() && in IsScalarPlusImmediate()
607 return base_.IsX() && regoffset_.IsX() && in IsScalarPlusScalar()
616 return base_.IsX() && regoffset_.IsZRegister() && in IsScalarPlusVector()
627 return base_.IsZRegister() && regoffset_.IsX() && in IsVectorPlusScalar()
645 VIXL_ASSERT(base_.IsX()); in GetScalarBase()
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| D | assembler-sve-aarch64.cc | 468 VIXL_ASSERT(rdn.IsX()); \
476 V(uqdecb, (rdn.IsX() ? UQDECB_r_rs_x : UQDECB_r_rs_uw)) \
477 V(uqdech, (rdn.IsX() ? UQDECH_r_rs_x : UQDECH_r_rs_uw)) \
478 V(uqdecw, (rdn.IsX() ? UQDECW_r_rs_x : UQDECW_r_rs_uw)) \
479 V(uqdecd, (rdn.IsX() ? UQDECD_r_rs_x : UQDECD_r_rs_uw)) \
480 V(uqincb, (rdn.IsX() ? UQINCB_r_rs_x : UQINCB_r_rs_uw)) \
481 V(uqinch, (rdn.IsX() ? UQINCH_r_rs_x : UQINCH_r_rs_uw)) \
482 V(uqincw, (rdn.IsX() ? UQINCW_r_rs_x : UQINCW_r_rs_uw)) \
483 V(uqincd, (rdn.IsX() ? UQINCD_r_rs_x : UQINCD_r_rs_uw))
2029 VIXL_ASSERT(rdn.IsX()); in decp()
[all …]
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| D | macro-assembler-sve-aarch64.cc | 252 VIXL_ASSERT(xd.IsX()); in Addvl()
253 VIXL_ASSERT(xn.IsX()); in Addvl()
309 VIXL_ASSERT(xd.IsX()); in CalculateSVEAddress()
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| D | assembler-aarch64.cc | 1148 VIXL_ASSERT(((emitop & LoadStorePairMask) != LDPSW_x) || rt.IsX()); in LoadStorePair()
2817 VIXL_ASSERT((index == 1) && vd.Is1D() && rn.IsX()); in fmov()
2825 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX()); in fmov()
4521 VIXL_ASSERT(vd.Is2D() == rn.IsX()); in dup()
4594 VIXL_ASSERT(rn.IsX()); in ins()
4634 VIXL_ASSERT(rd.IsX()); in umov()
4671 VIXL_ASSERT(rd.IsX()); in smov()
6285 return rt.IsX() ? LDR_x_lit : LDR_w_lit; in LoadLiteralOpFor()
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| D | registers-aarch64.h | 336 bool IsX() const { return IsRegister() && Is64Bits(); } in IsX() function
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| /third_party/node/deps/v8/src/baseline/arm64/ |
| D | baseline-assembler-arm64-inl.h | 528 DCHECK(lhs.IsX());
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | register-arm64.h | 158 bool IsX() const { return IsRegister() && Is64Bits(); } in IsX() function
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| D | assembler-arm64.cc | 1898 DCHECK(rn.IsX()); in ins()
1928 DCHECK(rd.IsX()); in smov()
2085 DCHECK(rd.IsX()); in umov()
2103 DCHECK_EQ(vd.Is2D(), rn.IsX()); in dup()
2655 DCHECK((index == 1) && vd.Is1D() && rn.IsX()); in fmov()
2661 DCHECK((index == 1) && vn.Is1D() && rd.IsX()); in fmov()
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| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| D | disasm-arm64.cc | 3615 if (reg.IsX() && (reg.code() == 27)) { in AppendRegisterNameToOutput()
3617 } else if (reg.IsX() && (reg.code() == 29)) { in AppendRegisterNameToOutput()
3619 } else if (reg.IsX() && (reg.code() == 30)) { in AppendRegisterNameToOutput()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-arm64.h | 707 bool IsX() const { return type_ == X_ARG; } in IsX() function
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| D | simulator-arm64.cc | 149 if (arg.IsX() && (index_x < 8)) { in CallImpl()
154 DCHECK(arg.IsD() || arg.IsX()); in CallImpl()
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| /third_party/node/src/ |
| D | README.md | 208 Generally, using `val.As<v8::X>()` is only valid if `val->IsX()` is true, and
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