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Searched refs:Latency (Results 1 – 25 of 152) sorted by relevance

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/third_party/node/deps/v8/src/compiler/backend/mips64/
Dinstruction-scheduler-mips64.cc421 enum Latency { enum
584 return Latency::MUL; in MulLatency()
586 return Latency::MUL + 1; in MulLatency()
593 latency = Latency::DMUL; in DmulLatency()
595 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
606 latency = Latency::MUH; in MulhLatency()
608 latency = Latency::MULT + Latency::MFHI; in MulhLatency()
619 latency = Latency::MUH; in MulhuLatency()
621 latency = Latency::MULTU + Latency::MFHI; in MulhuLatency()
632 latency = Latency::DMUH; in DMulhLatency()
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/third_party/node/deps/v8/src/compiler/backend/mips/
Dinstruction-scheduler-mips.cc396 enum Latency { enum
529 return (6 + 2 * Latency::BRANCH); in ClzLatency()
574 return Latency::MULT + 1; in MulLatency()
576 return Latency::MUL + 1; in MulLatency()
580 return Latency::MULT + 2; in MulLatency()
582 return Latency::MUL + 2; in MulLatency()
608 return latency + Latency::BRANCH + 2; in ShlPairLatency()
622 return latency + Latency::BRANCH + 2; in ShrPairLatency()
636 Latency::BRANCH + 6; in SarPairLatency()
689 return latency + Latency::MULTU + 2; in MuluLatency()
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/third_party/node/deps/v8/src/compiler/backend/riscv64/
Dinstruction-scheduler-riscv64.cc427 enum Latency { enum
585 return Latency::MUL32; in Mul32Latency()
587 return Latency::MUL32 + 1; in Mul32Latency()
592 int latency = Latency::DMULT + Latency::MOVF_LOW; in Mul64Latency()
600 int latency = Latency::MULT + Latency::MOVF_HIGH; in Mulh32Latency()
608 int latency = Latency::MULTU + Latency::MOVF_HIGH; in Mulhu32Latency()
616 int latency = Latency::DMULT + Latency::MOVF_HIGH; in Mulh64Latency()
625 return Latency::DIV32; in Div32Latency()
627 return Latency::DIV32 + 1; in Div32Latency()
633 return Latency::DIVU32; in Divu32Latency()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleA57WriteRes.td14 // Latency: #cyc
26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
36 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
38 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td14 // Latency: #cyc
25 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
34 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
35 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
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DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
36 let Latency = 4; let NumMicroOps = 4;
42 let Latency = 3; let NumMicroOps = 4;
48 let Latency = 3; let NumMicroOps = 2;
54 let Latency = 3; let NumMicroOps = 2;
60 let Latency = 3; let NumMicroOps = 2;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
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DAArch64SchedKryo.td64 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
65 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
67 { let Latency = 2; let NumMicroOps = 2; }
69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
72 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
74 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
77 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
78 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
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DAArch64SchedExynosM4.td133 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
134 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
136 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
139 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
140 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
141 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
144 M4UnitC]> { let Latency = 2;
148 M4UnitC]> { let Latency = 3;
151 M4UnitC]> { let Latency = 2;
153 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
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DAArch64SchedExynosM3.td108 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
110 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
113 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
114 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
117 M3UnitC]> { let Latency = 1;
121 M3UnitC]> { let Latency = 2;
124 M3UnitC]> { let Latency = 2;
126 def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
127 def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
144 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
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DAArch64SchedExynosM5.td133 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
134 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
136 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
139 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
140 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
141 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
143 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
147 M5UnitE]> { let Latency = 2;
151 M5UnitC]> { let Latency = 3;
154 M5UnitC]> { let Latency = 2;
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DAArch64SchedThunderX.td50 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
51 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
52 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
53 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
54 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
59 let Latency = 4;
64 let Latency = 4;
70 let Latency = 12;
75 let Latency = 14;
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DAArch64SchedA53.td58 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
59 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
60 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
63 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
66 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
67 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
70 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
71 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
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DAArch64SchedFalkorDetails.td20 // Latency: #cyc
35 let Latency = 2;
39 let Latency = 2;
43 let Latency = 3;
47 let Latency = 4;
54 def FalkorWr_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 2; }
55 def FalkorWr_IMUL32_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; }
56 def FalkorWr_IMUL64_1X_4cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; }
57 def FalkorWr_IMUL64_1X_5cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 5; }
58 def FalkorWr_1Z_0cyc : SchedWriteRes<[FalkorUnitZ]> { let Latency = 0; }
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
85 [11], // Latency = 7, Repeat rate = 1
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
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DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
58 [4, 1, 1, 1], // Latency = 1
64 [5, 1, 1], // Latency = 1 or 2
70 [17, 1, 1], // Latency=4..35, Repeat= 4..35
75 [11], // Latency = 8
79 [11, 1, 1], // Latency = 8
83 [7, 1, 1], // Latency = 4, Repeat rate = 1
88 [7, 1, 1], // Latency = 4, Repeat rate = 1
93 [7, 1, 1], // Latency = 4, Repeat rate = 1
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DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
53 [4, 1, 1, 1], // Latency = 1
59 [5, 1, 1], // Latency = 1 or 2
65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
70 [7, 1, 1], // Latency = 4, Repeat rate = 1
75 [7, 1, 1], // Latency = 4, Repeat rate = 1
80 [7, 1, 1], // Latency = 4, Repeat rate = 1
85 [4, 1, 1], // Latency = 1
90 [4, 1, 1], // Latency = 1
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DPPCScheduleP9.td139 let Latency = 1;
146 let Latency = 1;
153 let Latency = 1;
159 let Latency = 1;
164 let Latency = 1;
170 let Latency = 1;
175 let Latency = 1;
180 let Latency = 1;
185 let Latency = 1;
195 let Latency = 2;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SchedHaswell.td102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
144 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
171 let Latency = 2;
463 let Latency = 2;
468 let Latency = 6;
474 let Latency = 2;
478 let Latency = 2;
486 let Latency = 11;
491 let Latency = 17;
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DX86SchedSkylakeClient.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
164 let Latency = 2;
412 let Latency = 2;
417 let Latency = 6;
423 let Latency = 3;
427 let Latency = 2;
477 let Latency = 10;
482 let Latency = 16;
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DX86SchedBroadwell.td97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
167 let Latency = 2;
422 let Latency = 2;
427 let Latency = 6;
432 let Latency = 2;
436 let Latency = 2;
486 let Latency = 11;
491 let Latency = 16;
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DX86SchedSkylakeServer.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
165 let Latency = 2;
413 let Latency = 2;
418 let Latency = 6;
424 let Latency = 3;
428 let Latency = 2;
478 let Latency = 10;
483 let Latency = 16;
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DX86SchedSandyBridge.td92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
166 let Latency = 2;
433 let Latency = 2;
437 let Latency = 7;
442 let Latency = 3;
446 let Latency = 5;
468 let Latency = 11;
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DX86ScheduleAtom.td64 let Latency = RRLat;
71 let Latency = RMLat;
120 let Latency = 2;
124 let Latency = 2;
193 def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }
194 def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
455 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
456 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
458 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
488 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
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DX86ScheduleZnver2.td90 // 4 Cycles load-to use Latency is captured
93 // 7 Cycles vector load-to use Latency is captured
137 let Latency = Lat;
145 let Latency = !add(Lat, LoadLat);
158 let Latency = Lat;
166 let Latency = !add(Lat, LoadLat);
179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 8; }
243 let Latency = 4;
435 let Latency = 2;
439 let Latency = 5;
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DX86ScheduleSLM.td68 let Latency = Lat;
76 let Latency = !add(Lat, LoadLat);
88 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
95 def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
137 // FIXME Latency and NumMicrOps?
178 def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
179 def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; }
180 def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
181 def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }
182 def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
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