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Searched refs:LdSt (Results 1 – 20 of 20) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td55 def LdSt : ProcResource<1> { let BufferSize = 0; }
64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
DLanaiInstrInfo.cpp758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth()
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth()
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth()
768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth()
789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument
802 switch (LdSt.getOpcode()) { in getMemOperandWithOffset()
815 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
DLanaiInstrInfo.h70 bool getMemOperandWithOffset(const MachineInstr &LdSt,
75 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp563 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
565 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth()
571 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
573 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
576 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
579 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth()
580 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
581 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
DRISCVInstrInfo.h89 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument
265 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffset()
268 unsigned Opc = LdSt.getOpcode(); in getMemOperandWithOffset()
270 if (isDS(LdSt)) { in getMemOperandWithOffset()
272 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandWithOffset()
275 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
290 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandWithOffset()
292 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandWithOffset()
302 if (LdSt.mayLoad()) in getMemOperandWithOffset()
303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandWithOffset()
[all …]
DSIInstrInfo.h184 bool getMemOperandWithOffset(const MachineInstr &LdSt,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1981 bool AArch64InstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument
1985 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffset()
1989 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
1995 assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); in getMemOperandWithOffsetWidth()
1997 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
1999 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth()
2000 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
2002 } else if (LdSt.getNumExplicitOperands() == 4) { in getMemOperandWithOffsetWidth()
2004 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth()
[all …]
DAArch64InstrInfo.h126 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h362 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
DPPCInstrInfo.cpp4260 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
4262 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth()
4266 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
4268 if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg()) in getMemOperandWithOffsetWidth()
4271 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
4274 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth()
4275 Offset = LdSt.getOperand(1).getImm(); in getMemOperandWithOffsetWidth()
4276 BaseReg = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h207 bool getMemOperandWithOffset(const MachineInstr &LdSt,
DHexagonInstrInfo.cpp2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
2947 BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize); in getMemOperandWithOffset()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.h294 bool getMemOperandWithOffset(const MachineInstr &LdSt,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.h827 OperandMIPS32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
DIceTargetLoweringARM32.h1124 OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
DIceTargetLoweringMIPS32.cpp5301 const Inst *LdSt, in formAddressingMode() argument
5311 LdSt->dumpDecorated(Func); in formAddressingMode()
DIceTargetLoweringARM32.cpp5564 const Inst *LdSt, in formAddressingMode() argument
5577 LdSt->dumpDecorated(Func); in formAddressingMode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1044 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
1045 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1050 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) in SelectAddrMode6Offset()
DARMScheduleR52.td551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue