| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
456 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
457 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
458 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
464 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
466 def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>;
490 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>;
494 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>;
506 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
509 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
[all …]
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| D | HexagonCopyToCombine.cpp | 761 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
772 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
780 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
787 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
795 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
802 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
860 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
879 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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| D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| D | HexagonFrameLowering.cpp | 977 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
979 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.h | 52 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
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| D | AVRRegisterInfo.cpp | 268 unsigned &LoReg, in splitReg() argument
272 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 4696 unsigned LoReg, ROpc, MOpc; in Select() local
4700 LoReg = X86::AL; in Select()
4705 LoReg = X86::AX; in Select()
4710 LoReg = X86::EAX; in Select()
4715 LoReg = X86::RAX; in Select()
4730 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
4790 unsigned SrcReg, LoReg, HiReg; in Select() local
4795 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
4799 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
4837 assert(LoReg && "Register for low half is not defined!"); in Select()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 186 unsigned LoReg = 0; member
1594 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 || in computeBase()
1616 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg) in computeBase()
1727 Addr.Base.LoReg = BaseLo.getReg(); in processBaseWithConstOffset()
1775 << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";); in promoteConstantOffsetToImm()
1831 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg || in promoteConstantOffsetToImm()
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| D | AMDGPUInstructionSelector.cpp | 1464 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
1467 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg) in selectG_CONSTANT()
1474 .addReg(LoReg) in selectG_CONSTANT()
1675 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
1678 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_PTR_MASK()
1684 .addReg(LoReg) in selectG_PTR_MASK()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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| D | MipsSEInstrInfo.cpp | 814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
843 .addReg(LoReg); in expandBuildPairF64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1135 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
1143 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg) in emitReadCycleWidePseudo()
1171 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
1182 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
1204 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
1213 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) in emitBuildPairF64Pseudo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 11341 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
11345 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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