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Searched refs:MI1 (Results 1 – 22 of 22) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
312 Info.MI1 = nullptr; in handleUse()
354 OpInfo.MI1 = &MI; in handleMiddleInst()
356 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
359 OpInfo.MI1 = &MI; in handleMiddleInst()
368 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
371 OpInfo.MI1 = &MI; in handleMiddleInst()
376 OpInfo.MI1 = &MI; in handleMiddleInst()
412 << '\t' << MI << '\t' << *Info.MI1 << '\t' in handleADRP()
414 AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0}); in handleADRP()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
469 (MI1->getOpcode() == Mips::LW_MM) || in ReduceXWtoXWP()
470 (MI1->getOpcode() == Mips::LW16_MM); in ReduceXWtoXWP()
472 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry)) in ReduceXWtoXWP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp457 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
495 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
496 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
505 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
506 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
509 << printMBBReference(*MI1->getParent()) << " " << *MI1); in hoistAndMergeSGPRInits()
510 MergedInstrs.insert(MI1); in hoistAndMergeSGPRInits()
516 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(), in hoistAndMergeSGPRInits()
524 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
527 << printMBBReference(*MI1->getParent()) << " " << *MI1 in hoistAndMergeSGPRInits()
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DAMDGPUSubtarget.cpp779 MachineInstr &MI1 = *SUa->getInstr(); in apply() local
780 if ((TII->isVMEM(MI1) && TII->isVMEM(MI2)) || in apply()
781 (TII->isFLAT(MI1) && TII->isFLAT(MI2)) || in apply()
782 (TII->isSMRD(MI1) && TII->isSMRD(MI2)) || in apply()
783 (TII->isDS(MI1) && TII->isDS(MI2))) { in apply()
DSIInstrInfo.cpp401 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, in memOpsHaveSameBasePtr() argument
413 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
416 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr()
425 const MachineFunction &MF = *MI1.getParent()->getParent(); in memOpsHaveSameBasePtr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp420 const MachineInstr &MI1, in produceSameValue() argument
422 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
676 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
679 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
684 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
691 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
697 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
699 std::swap(MI1, MI2); in hasReassociableSibling()
705 return MI1->getOpcode() == AssocOpcode && in hasReassociableSibling()
706 hasReassociableOperands(*MI1, MBB) && in hasReassociableSibling()
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DDFAPacketizer.cpp301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
307 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp146 MachineInstr &MI1 = *SU.getInstr(); in apply() local
148 bool IsStoreMI1 = MI1.mayStore(); in apply()
149 bool IsLoadMI1 = MI1.mayLoad(); in apply()
150 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) in apply()
DHexagonVLIWPacketizer.cpp959 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
963 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
968 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
1016 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
1021 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1022 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
DHexagonInstrInfo.h398 bool isToBeScheduledASAP(const MachineInstr &MI1,
410 bool addLatencyToSchedule(const MachineInstr &MI1,
DHexagonVLIWPacketizer.h134 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
DHexagonInstrInfo.cpp2615 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP() argument
2617 if (mayBeCurLoad(MI1)) { in isToBeScheduledASAP()
2619 Register DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2627 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2628 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
2934 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule() argument
2936 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
2937 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
DHexagonPatterns.td772 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
774 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp277 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift() argument
403 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
DX86ISelLowering.h1460 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DDFAPacketizer.h190 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
DTargetInstrInfo.h543 const MachineInstr &MI1,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp316 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
317 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
DARMBaseInstrInfo.cpp1742 const MachineInstr &MI1, in produceSameValue() argument
1755 if (MI1.getOpcode() != Opcode) in produceSameValue()
1757 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1761 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1793 if (MI1.getOpcode() != Opcode) in produceSameValue()
1795 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1799 Register Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1817 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1824 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
DARMBaseInstrInfo.h237 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
/third_party/openssl/crypto/perlasm/
Ds390x.pm30 MI1 => [qw(risbgn)],
/third_party/node/deps/openssl/openssl/crypto/perlasm/
Ds390x.pm30 MI1 => [qw(risbgn)],