/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMInstPrinter.cpp | 101 const MCOperand &MO1 = MI->getOperand(1); in printInst() local 112 printRegName(O, MO1.getReg()); in printInst() 124 const MCOperand &MO1 = MI->getOperand(1); in printInst() local 134 printRegName(O, MO1.getReg()); in printInst() 354 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local 355 if (MO1.isExpr()) { in printThumbLdrLabelOperand() 356 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand() 362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand() 384 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local 388 printRegName(O, MO1.getReg()); in printSORegRegOperand() [all …]
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D | ARMMCCodeEmitter.cpp | 601 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local 605 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues() 936 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local 938 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() 1187 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local 1189 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue() 1254 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getLdStSORegOpValue() local 1257 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() 1291 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode2OffsetOpValue() local 1292 unsigned Imm = MO1.getImm(); in getAddrMode2OffsetOpValue() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86OptimizeLEAs.cpp | 67 static inline bool isIdenticalOp(const MachineOperand &MO1, 72 static bool isSimilarDispOp(const MachineOperand &MO1, 201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument 203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp() 204 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg())); in isIdenticalOp() 214 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument 216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp() 218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp() 219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp() 220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp() [all …]
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D | X86FloatingPoint.cpp | 1460 const MachineOperand &MO1 = MI.getOperand(1); in handleSpecialFP() local 1462 bool KillsSrc = MI.killsRegister(MO1.getReg()); in handleSpecialFP() 1466 unsigned SrcFP = getFPReg(MO1); in handleSpecialFP()
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D | X86InstrInfo.cpp | 5557 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand() local 5558 if (MO1.getImm() == 0) { in unfoldMemoryOperand() 5571 MO1.ChangeToRegister(MO0.getReg(), false); in unfoldMemoryOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ExpandPseudoInsts.cpp | 483 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local 484 unsigned Flags = MO1.getTargetFlags(); in expandMI() 491 if (MO1.isGlobal()) { in expandMI() 492 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags); in expandMI() 493 } else if (MO1.isSymbol()) { in expandMI() 494 MIB.addExternalSymbol(MO1.getSymbolName(), Flags); in expandMI() 496 assert(MO1.isCPI() && in expandMI() 498 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI() 523 if (MO1.isGlobal()) { in expandMI() 524 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/ |
D | MSP430MCCodeEmitter.cpp | 123 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local 124 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue() 125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue() 267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
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D | AArch64InstPrinter.cpp | 1097 const MCOperand MO1 = MI->getOperand(OpNum + 1); in printAMIndexedWB() local 1099 if (MO1.isImm()) { in printAMIndexedWB() 1100 O << ", #" << formatImm(MO1.getImm() * Scale); in printAMIndexedWB() 1102 assert(MO1.isExpr() && "Unexpected operand type!"); in printAMIndexedWB() 1104 MO1.getExpr()->print(O, &MAI); in printAMIndexedWB()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonAsmPrinter.cpp | 462 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local 463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction() 464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
D | HexagonAsmParser.cpp | 1223 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst() argument 1228 TmpInst.addOperand(MO1); in makeCombineInst() 1584 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local 1592 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction() 1599 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local 1601 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction() 1607 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 1475 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local 1476 auto Flags = MO1.getTargetFlags(); in ExpandMI() 1477 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI() 1533 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local 1534 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI() 1535 unsigned TF = MO1.getTargetFlags(); in ExpandMI() 1546 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) in ExpandMI() 1551 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) in ExpandMI()
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D | ARMAsmPrinter.cpp | 938 const MachineOperand &MO1 = MI->getOperand(1); in EmitJumpTableAddrs() local 939 unsigned JTI = MO1.getIndex(); in EmitJumpTableAddrs() 984 const MachineOperand &MO1 = MI->getOperand(1); in EmitJumpTableInsts() local 985 unsigned JTI = MO1.getIndex(); in EmitJumpTableInsts() 1014 const MachineOperand &MO1 = MI->getOperand(1); in EmitJumpTableTBInst() local 1015 unsigned JTI = MO1.getIndex(); in EmitJumpTableTBInst()
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D | ARMBaseInstrInfo.cpp | 1761 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue() local 1762 if (MO0.getOffset() != MO1.getOffset()) in produceSameValue() 1772 return MO0.getGlobal() == MO1.getGlobal(); in produceSameValue() 1777 int CPI1 = MO1.getIndex(); in produceSameValue() 1817 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue() local 1818 if (!MO0.isIdenticalTo(MO1)) in produceSameValue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | MachineVerifier.cpp | 2231 const MachineOperand &MO1 = Phi.getOperand(I + 1); in checkPHIOps() local 2232 if (!MO1.isMBB()) { in checkPHIOps() 2233 report("Expected PHI operand to be a basic block", &MO1, I + 1); in checkPHIOps() 2237 const MachineBasicBlock &Pre = *MO1.getMBB(); in checkPHIOps() 2239 report("PHI input is not a predecessor block", &MO1, I + 1); in checkPHIOps()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
D | LegalizerHelper.cpp | 1000 MachineOperand &MO1 = MI.getOperand(1); in narrowScalar() local 1001 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg()); in narrowScalar() 1002 MO1.setReg(TruncMIB->getOperand(0).getReg()); in narrowScalar()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 416 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local 418 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr() 421 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()
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