| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 102 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
115 printRegName(O, MO2.getReg()); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
385 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
397 printRegName(O, MO2.getReg()); in printSORegRegOperand()
405 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
410 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
[all …]
|
| D | ARMMCCodeEmitter.cpp | 937 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
939 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1255 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1258 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1259 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1349 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1364 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1512 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1513 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 68 const MachineOperand &MO2);
73 const MachineOperand &MO2);
202 const MachineOperand &MO2) { in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
215 const MachineOperand &MO2) { in isSimilarDispOp() argument
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
221 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/ |
| D | MSP430MCCodeEmitter.cpp | 127 const MCOperand &MO2 = MI.getOperand(Op + 1); in getMemOpValue() local
128 if (MO2.isImm()) { in getMemOpValue()
130 return ((unsigned)MO2.getImm() << 4) | Reg; in getMemOpValue()
133 assert(MO2.isExpr() && "Expr operand expected"); in getMemOpValue()
146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), in getMemOpValue()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1224 MCOperand &MO2) { in makeCombineInst() argument
1229 TmpInst.addOperand(MO2); in makeCombineInst()
1585 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1587 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1592 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1606 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1607 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 952 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
953 switch (MO2.getReg()) { in reverseBranchCondition()
955 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
958 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
|
| D | SIInstrInfo.cpp | 417 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr() local
418 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
422 auto Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 452 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
453 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 948 for (const MachineOperand &MO2 : MI.operands()) { in collectVRegUses() local
949 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 1004 MachineOperand &MO2 = MI.getOperand(0); in narrowScalar() local
1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt}); in narrowScalar()
1008 MO2.setReg(DstExt); in narrowScalar()
|