1 /******************************************************************************
2 * @file mpu_armv8.h
3 * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
4 * @version V5.9.0
5 * @date 11. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV8_H
32 #define ARM_MPU_ARMV8_H
33
34 /** \brief Attribute for device memory (outer only) */
35 #define ARM_MPU_ATTR_DEVICE ( 0U )
36
37 /** \brief Attribute for non-cacheable, normal memory */
38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39
40 /** \brief Attribute for Normal memory, Outer and Inner cacheability.
41 * \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
42 * \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
43 * \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
44 * \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
45 */
46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
48
49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51
52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54
55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57
58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60
61 /** \brief Normal memory outer-cacheable and inner-cacheable attributes
62 * WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
63 */
64 #define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
65 #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
66 #define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
67 #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
68 #define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
69 #define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
70 #define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
71 #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
72 #define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
73 #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
74 #define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
75 #define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
76 #define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
77 #define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
78 #define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
79 #define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
80 #define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
81 #define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
82 #define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
83 #define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
84 #define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
85 #define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
86 #define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
87 #define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
88 #define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
89 #define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
90
91 /** \brief Memory Attribute
92 * \param O Outer memory attributes
93 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
94 */
95 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
96
97 /* \brief Specifies MAIR_ATTR number */
98 #define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
99
100 /**
101 * Shareability
102 */
103 /** \brief Normal memory, non-shareable */
104 #define ARM_MPU_SH_NON (0U)
105
106 /** \brief Normal memory, outer shareable */
107 #define ARM_MPU_SH_OUTER (2U)
108
109 /** \brief Normal memory, inner shareable */
110 #define ARM_MPU_SH_INNER (3U)
111
112 /**
113 * Access permissions
114 * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
115 */
116 /** \brief Normal memory, read/write */
117 #define ARM_MPU_AP_RW (0U)
118
119 /** \brief Normal memory, read-only */
120 #define ARM_MPU_AP_RO (1U)
121
122 /** \brief Normal memory, any privilege level */
123 #define ARM_MPU_AP_NP (1U)
124
125 /** \brief Normal memory, privileged access only */
126 #define ARM_MPU_AP_PO (0U)
127
128 /*
129 * Execute-never
130 * XN = Execute-never, EX = Executable
131 */
132 /** \brief Normal memory, Execution only permitted if read permitted */
133 #define ARM_MPU_XN (1U)
134
135 /** \brief Normal memory, Execution only permitted if read permitted */
136 #define ARM_MPU_EX (0U)
137
138 /** \brief Memory access permissions
139 * \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
140 * \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
141 */
142 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
143
144 /** \brief Region Base Address Register value
145 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
146 * \param SH Defines the Shareability domain for this memory region.
147 * \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
148 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
149 * \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
150 */
151 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
152 (((BASE) & MPU_RBAR_BASE_Msk) | \
153 (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
154 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
155 (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
156
157 /** \brief Region Limit Address Register value
158 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
159 * \param IDX The attribute index to be associated with this memory region.
160 */
161 #define ARM_MPU_RLAR(LIMIT, IDX) \
162 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
163 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
164 (MPU_RLAR_EN_Msk))
165
166 #if defined(MPU_RLAR_PXN_Pos)
167
168 /** \brief Region Limit Address Register with PXN value
169 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
170 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
171 * \param IDX The attribute index to be associated with this memory region.
172 */
173 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
174 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
175 (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
176 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
177 (MPU_RLAR_EN_Msk))
178
179 #endif
180
181 /**
182 * Struct for a single MPU Region
183 */
184 typedef struct {
185 uint32_t RBAR; /*!< Region Base Address Register value */
186 uint32_t RLAR; /*!< Region Limit Address Register value */
187 } ARM_MPU_Region_t;
188
189 /**
190 \brief Read MPU Type Register
191 \return Number of MPU regions
192 */
ARM_MPU_TYPE()193 __STATIC_INLINE uint32_t ARM_MPU_TYPE()
194 {
195 return ((MPU->TYPE) >> 8);
196 }
197
198 /** Enable the MPU.
199 * \param MPU_Control Default access permissions for unconfigured regions.
200 */
ARM_MPU_Enable(uint32_t MPU_Control)201 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
202 {
203 __DMB();
204 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
205 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
206 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
207 #endif
208 __DSB();
209 __ISB();
210 }
211
212 /** Disable the MPU.
213 */
ARM_MPU_Disable(void)214 __STATIC_INLINE void ARM_MPU_Disable(void)
215 {
216 __DMB();
217 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
218 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
219 #endif
220 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
221 __DSB();
222 __ISB();
223 }
224
225 #ifdef MPU_NS
226 /** Enable the Non-secure MPU.
227 * \param MPU_Control Default access permissions for unconfigured regions.
228 */
ARM_MPU_Enable_NS(uint32_t MPU_Control)229 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
230 {
231 __DMB();
232 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
233 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
234 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
235 #endif
236 __DSB();
237 __ISB();
238 }
239
240 /** Disable the Non-secure MPU.
241 */
ARM_MPU_Disable_NS(void)242 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
243 {
244 __DMB();
245 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
246 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
247 #endif
248 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
249 __DSB();
250 __ISB();
251 }
252 #endif
253
254 /** Set the memory attribute encoding to the given MPU.
255 * \param mpu Pointer to the MPU to be configured.
256 * \param idx The attribute index to be set [0-7]
257 * \param attr The attribute value to be set.
258 */
ARM_MPU_SetMemAttrEx(MPU_Type * mpu,uint8_t idx,uint8_t attr)259 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
260 {
261 const uint8_t reg = idx / 4U;
262 const uint32_t pos = ((idx % 4U) * 8U);
263 const uint32_t mask = 0xFFU << pos;
264
265 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
266 return; // invalid index
267 }
268
269 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
270 }
271
272 /** Set the memory attribute encoding.
273 * \param idx The attribute index to be set [0-7]
274 * \param attr The attribute value to be set.
275 */
ARM_MPU_SetMemAttr(uint8_t idx,uint8_t attr)276 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
277 {
278 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
279 }
280
281 #ifdef MPU_NS
282 /** Set the memory attribute encoding to the Non-secure MPU.
283 * \param idx The attribute index to be set [0-7]
284 * \param attr The attribute value to be set.
285 */
ARM_MPU_SetMemAttr_NS(uint8_t idx,uint8_t attr)286 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
287 {
288 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
289 }
290 #endif
291
292 /** Clear and disable the given MPU region of the given MPU.
293 * \param mpu Pointer to MPU to be used.
294 * \param rnr Region number to be cleared.
295 */
ARM_MPU_ClrRegionEx(MPU_Type * mpu,uint32_t rnr)296 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
297 {
298 mpu->RNR = rnr;
299 mpu->RLAR = 0U;
300 }
301
302 /** Clear and disable the given MPU region.
303 * \param rnr Region number to be cleared.
304 */
ARM_MPU_ClrRegion(uint32_t rnr)305 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
306 {
307 ARM_MPU_ClrRegionEx(MPU, rnr);
308 }
309
310 #ifdef MPU_NS
311 /** Clear and disable the given Non-secure MPU region.
312 * \param rnr Region number to be cleared.
313 */
ARM_MPU_ClrRegion_NS(uint32_t rnr)314 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
315 {
316 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
317 }
318 #endif
319
320 /** Configure the given MPU region of the given MPU.
321 * \param mpu Pointer to MPU to be used.
322 * \param rnr Region number to be configured.
323 * \param rbar Value for RBAR register.
324 * \param rlar Value for RLAR register.
325 */
ARM_MPU_SetRegionEx(MPU_Type * mpu,uint32_t rnr,uint32_t rbar,uint32_t rlar)326 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
327 {
328 mpu->RNR = rnr;
329 mpu->RBAR = rbar;
330 mpu->RLAR = rlar;
331 }
332
333 /** Configure the given MPU region.
334 * \param rnr Region number to be configured.
335 * \param rbar Value for RBAR register.
336 * \param rlar Value for RLAR register.
337 */
ARM_MPU_SetRegion(uint32_t rnr,uint32_t rbar,uint32_t rlar)338 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
339 {
340 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
341 }
342
343 #ifdef MPU_NS
344 /** Configure the given Non-secure MPU region.
345 * \param rnr Region number to be configured.
346 * \param rbar Value for RBAR register.
347 * \param rlar Value for RLAR register.
348 */
ARM_MPU_SetRegion_NS(uint32_t rnr,uint32_t rbar,uint32_t rlar)349 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
350 {
351 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
352 }
353 #endif
354
355 /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
356 * \param dst Destination data is copied to.
357 * \param src Source data is copied from.
358 * \param len Amount of data words to be copied.
359 */
ARM_MPU_OrderedMemcpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)360 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
361 {
362 uint32_t i;
363 for (i = 0U; i < len; ++i)
364 {
365 dst[i] = src[i];
366 }
367 }
368
369 /** Load the given number of MPU regions from a table to the given MPU.
370 * \param mpu Pointer to the MPU registers to be used.
371 * \param rnr First region number to be configured.
372 * \param table Pointer to the MPU configuration table.
373 * \param cnt Amount of regions to be configured.
374 */
ARM_MPU_LoadEx(MPU_Type * mpu,uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)375 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
376 {
377 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
378 if (cnt == 1U) {
379 mpu->RNR = rnr;
380 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
381 } else {
382 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
383 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
384
385 mpu->RNR = rnrBase;
386 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
387 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
388 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
389 table += c;
390 cnt -= c;
391 rnrOffset = 0U;
392 rnrBase += MPU_TYPE_RALIASES;
393 mpu->RNR = rnrBase;
394 }
395
396 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
397 }
398 }
399
400 /** Load the given number of MPU regions from a table.
401 * \param rnr First region number to be configured.
402 * \param table Pointer to the MPU configuration table.
403 * \param cnt Amount of regions to be configured.
404 */
ARM_MPU_Load(uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)405 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
406 {
407 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
408 }
409
410 #ifdef MPU_NS
411 /** Load the given number of MPU regions from a table to the Non-secure MPU.
412 * \param rnr First region number to be configured.
413 * \param table Pointer to the MPU configuration table.
414 * \param cnt Amount of regions to be configured.
415 */
ARM_MPU_Load_NS(uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)416 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
417 {
418 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
419 }
420 #endif
421
422 #endif
423
424