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Searched refs:NewOpcode (Results 1 – 25 of 33) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp84 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
87 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
90 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
93 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
96 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
102 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
DHexagonVLIWPacketizer.cpp455 int NewOpcode; in promoteToDotNew() local
457 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
459 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
460 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
465 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
466 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
884 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
885 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
DHexagonInstrInfo.cpp1534 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); in reverseBranchCondition() local
1535 Cond[0].setImm(NewOpcode); in reverseBranchCondition()
3667 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); in getDotNewPredOp() local
3668 if (NewOpcode >= 0) in getDotNewPredOp()
3669 return NewOpcode; in getDotNewPredOp()
4372 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); in invertAndChangeJumpTarget() local
4381 NewOpcode = reversePrediction(NewOpcode); in invertAndChangeJumpTarget()
4383 MI.setDesc(get(NewOpcode)); in invertAndChangeJumpTarget()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp76 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
83 if (!(NewOpcode = VCMPOpcodeToVPT(Def->getOpcode()))) in findVCMPToFoldIntoVPST()
144 unsigned NewOpcode; in InsertVPTBlocks() local
145 MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, RDA, NewOpcode); in InsertVPTBlocks()
148 MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode)); in InsertVPTBlocks()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp389 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
412 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
423 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
430 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
DX86InstrInfo.cpp3575 unsigned NewOpcode = 0; in optimizeCompareInstr() local
3578 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
3579 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
3580 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
3581 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
3582 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
3583 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
3584 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
3585 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
3586 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
DX86MCInstLower.cpp316 unsigned NewOpcode = 0; in SimplifyMOVSX() local
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
331 NewOpcode = X86::CDQE; in SimplifyMOVSX()
335 if (NewOpcode != 0) { in SimplifyMOVSX()
337 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
253 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
254 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
441 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
459 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDILCFGStructurizer.cpp222 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
224 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
226 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
227 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
230 MachineBasicBlock::iterator I, int NewOpcode,
457 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
459 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
466 int NewOpcode, in insertInstrBefore() argument
469 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
479 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
DSIShrinkInstructions.cpp292 unsigned NewOpcode = in shrinkMIMG() local
295 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
DSIInstrInfo.cpp4836 unsigned NewOpcode = getVALUOp(Inst); in moveToVALU() local
4915 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALU()
4921 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALU()
4927 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALU()
4933 NewOpcode = AMDGPU::V_LSHLREV_B64; in moveToVALU()
4939 NewOpcode = AMDGPU::V_ASHRREV_I64; in moveToVALU()
4945 NewOpcode = AMDGPU::V_LSHRREV_B64; in moveToVALU()
5007 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { in moveToVALU()
5015 const MCInstrDesc &NewDesc = get(NewOpcode); in moveToVALU()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp193 int NewOpcode = -1; in encodeInstruction() local
196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
197 if (NewOpcode == -1) in encodeInstruction()
198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
204 if (NewOpcode == -1) in encodeInstruction()
205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
207 if (NewOpcode != -1) { in encodeInstruction()
211 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp604 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
608 if (!NewOpcode) { in emitEpilogue()
613 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
614 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
617 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
DSystemZInstrInfo.cpp66 unsigned NewOpcode) const { in splitMove()
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
126 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
127 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
966 unsigned NewOpcode; in convertToThreeAddress() local
968 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
971 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
973 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
DSystemZInstrInfo.h164 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.cpp233 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
238 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp743 unsigned NewOpcode; in applyCombineIndexedLoadStore() local
746 NewOpcode = TargetOpcode::G_INDEXED_LOAD; in applyCombineIndexedLoadStore()
749 NewOpcode = TargetOpcode::G_INDEXED_SEXTLOAD; in applyCombineIndexedLoadStore()
752 NewOpcode = TargetOpcode::G_INDEXED_ZEXTLOAD; in applyCombineIndexedLoadStore()
755 NewOpcode = TargetOpcode::G_INDEXED_STORE; in applyCombineIndexedLoadStore()
761 auto MIB = MIRBuilder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp1561 std::string NewOpcode; in ParseInstruction() local
1563 NewOpcode = Name; in ParseInstruction()
1564 NewOpcode += '+'; in ParseInstruction()
1565 Name = NewOpcode; in ParseInstruction()
1568 NewOpcode = Name; in ParseInstruction()
1569 NewOpcode += '-'; in ParseInstruction()
1570 Name = NewOpcode; in ParseInstruction()
1576 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1584 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp533 int NewOpcode = in convertMIMGInst() local
535 if (NewOpcode == -1) in convertMIMGInst()
541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; in convertMIMGInst()
571 MI.setOpcode(NewOpcode); in convertMIMGInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp6344 unsigned NewOpcode; in PeepholePPC64ZExt() local
6348 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
6349 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
6350 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
6351 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
6352 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
6353 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
6354 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
6355 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
6356 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
DPPCAsmPrinter.cpp1134 unsigned NewOpcode = in EmitInstruction() local
1138 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
1148 unsigned NewOpcode = in EmitInstruction() local
1154 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
DPPCRegisterInfo.cpp1152 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
1153 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h753 int64_t NewOpcode = MatchTable[CurrentIdx++]; in executeMatchTable() local
759 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); in executeMatchTable()
763 << NewOpcode << ")\n"); in executeMatchTable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsDelaySlotFiller.cpp566 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
567 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()

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