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Searched refs:NoReg (Results 1 – 18 of 18) sorted by relevance

/third_party/vixl/src/aarch64/
Doperands-aarch64.cc141 reg_(NoReg), in Operand()
148 reg_(NoReg), in Operand()
179 bool Operand::IsImmediate() const { return reg_.Is(NoReg); } in IsImmediate()
227 : base_(NoReg), in MemOperand()
228 regoffset_(NoReg), in MemOperand()
238 regoffset_(NoReg), in MemOperand()
287 regoffset_(NoReg), in MemOperand()
334 if (regoffset_.Is(NoReg)) { in IsEquivalentToPlainRegister()
347 return (addrmode_ == Offset) && regoffset_.Is(NoReg); in IsImmediateOffset()
352 return (addrmode_ == Offset) && !regoffset_.Is(NoReg); in IsRegisterOffset()
[all …]
Dregisters-aarch64.h838 const Register NoReg;
972 const CPURegister& reg3 = NoReg,
973 const CPURegister& reg4 = NoReg,
974 const CPURegister& reg5 = NoReg,
975 const CPURegister& reg6 = NoReg,
976 const CPURegister& reg7 = NoReg,
977 const CPURegister& reg8 = NoReg) {
1052 const CPURegister& reg3 = NoReg,
1053 const CPURegister& reg4 = NoReg,
1054 const CPURegister& reg5 = NoReg,
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Doperands-aarch64.h488 regoffset_(NoReg), in base_()
507 regoffset_(NoReg), in base_()
Dmacro-assembler-aarch64.cc585 VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) && in Emit()
2242 PushHelper(2, size, src, src, NoReg, NoReg); in Emit()
2246 PushHelper(1, size, src, NoReg, NoReg, NoReg); in Emit()
Dmacro-assembler-aarch64.h961 const CPURegister& src1 = NoReg,
962 const CPURegister& src2 = NoReg,
963 const CPURegister& src3 = NoReg);
965 const CPURegister& dst1 = NoReg,
966 const CPURegister& dst2 = NoReg,
967 const CPURegister& dst3 = NoReg);
1171 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1);
8446 const Register& reg2 = NoReg,
8447 const Register& reg3 = NoReg,
8448 const Register& reg4 = NoReg);
[all …]
Dassembler-aarch64.cc2026 VIXL_ASSERT(!addr.GetRegisterOffset().Is(NoReg) || in LoadStoreStructVerify()
/third_party/vixl/src/aarch32/
Doperands-aarch32.h57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) { in Operand()
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) { in Operand()
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) { in Operand()
641 rm_(NoReg), in rn_()
658 rm_(NoReg), in rn_()
668 rm_(NoReg), in rn_()
Dinstructions-aarch32.h418 const Register NoReg; variable
Dmacro-assembler-aarch32.h986 CPURegister reg1 = NoReg, in Assembler()
987 CPURegister reg2 = NoReg, in Assembler()
988 CPURegister reg3 = NoReg, in Assembler()
989 CPURegister reg4 = NoReg); in Assembler()
13430 const Register& reg2 = NoReg, in Assembler()
13431 const Register& reg3 = NoReg, in Assembler()
13432 const Register& reg4 = NoReg) { in Assembler()
13448 const Register& reg2 = NoReg, in Assembler()
13449 const Register& reg3 = NoReg, in Assembler()
13450 const Register& reg4 = NoReg) { in Assembler()
/third_party/node/deps/v8/src/codegen/arm64/
Dregister-arm64.h440 constexpr Register NoReg = Register::no_reg();
443 constexpr Register no_reg = NoReg;
515 const CPURegister& reg3 = NoReg, const CPURegister& reg4 = NoReg,
516 const CPURegister& reg5 = NoReg, const CPURegister& reg6 = NoReg,
517 const CPURegister& reg7 = NoReg, const CPURegister& reg8 = NoReg);
Dassembler-arm64-inl.h239 Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
243 : immediate_(t, rmode), reg_(NoReg) {}
271 DCHECK_IMPLIES(heap_object_request_.has_value(), reg_ == NoReg);
284 return reg_ == NoReg && !IsHeapObjectRequest();
365 : base_(NoReg),
366 regoffset_(NoReg),
375 regoffset_(NoReg),
416 : base_(base), regoffset_(NoReg), addrmode_(addrmode) {
453 return (addrmode_ == Offset) && regoffset_ == NoReg;
457 return (addrmode_ == Offset) && regoffset_ != NoReg;
Dmacro-assembler-arm64.h500 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1);
818 void Push(const CPURegister& src0, const CPURegister& src1 = NoReg,
819 const CPURegister& src2 = NoReg, const CPURegister& src3 = NoReg);
822 const CPURegister& src4, const CPURegister& src5 = NoReg,
823 const CPURegister& src6 = NoReg, const CPURegister& src7 = NoReg);
825 void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg,
826 const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg);
829 const CPURegister& dst4, const CPURegister& dst5 = NoReg,
830 const CPURegister& dst6 = NoReg, const CPURegister& dst7 = NoReg);
1144 void AssertFPCRState(Register fpcr = NoReg);
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Dmacro-assembler-arm64.cc981 DCHECK((reg == NoReg || type >= kBranchTypeFirstUsingReg) && in B()
1166 PushHelper(2, src.SizeInBytes(), src, src, NoReg, NoReg); in PushMultipleTimes()
1171 PushHelper(1, src.SizeInBytes(), src, NoReg, NoReg, NoReg); in PushMultipleTimes()
3432 CPURegister pcs[kPrintfMaxArgCount] = {NoReg, NoReg, NoReg, NoReg}; in TruncateDoubleToI()
Dassembler-arm64.cc2319 DCHECK(addr.regoffset() != NoReg || addr.offset() == offset); in LoadStoreStructVerify()
/third_party/vixl/test/aarch64/
Dtest-abi.cc71 GenericOperand found(NoReg); in TEST()
72 GenericOperand expected(NoReg); in TEST()
Dtest-api-aarch64.cc193 VIXL_CHECK(NoReg.Is(NoVReg)); in TEST()
194 VIXL_CHECK(NoVReg.Is(NoReg)); in TEST()
196 VIXL_CHECK(NoVReg.Is(NoReg)); in TEST()
197 VIXL_CHECK(NoReg.Is(NoVReg)); in TEST()
199 VIXL_CHECK(NoReg.Is(NoCPUReg)); in TEST()
200 VIXL_CHECK(NoCPUReg.Is(NoReg)); in TEST()
208 VIXL_CHECK(NoReg.IsNone()); in TEST()
382 VIXL_CHECK(!NoReg.IsValid()); in TEST()
453 VIXL_CHECK(!static_cast<CPURegister>(NoReg).IsValid()); in TEST()
1245 temps.Include(NoReg); in TEST()
Dtest-utils-aarch64.cc551 Register first = NoReg; in Clobber()
/third_party/node/deps/v8/src/regexp/arm64/
Dregexp-macro-assembler-arm64.cc1593 Register result = NoReg; in GetRegister()