| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
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| D | ExecutionDomainFix.cpp | 71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
92 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
160 LiveRegs.assign(NumRegs, nullptr); in enterBasicBlock()
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
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| D | LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
564 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { in runOnBlock() argument
615 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
625 const unsigned NumRegs = TRI->getNumRegs(); in runOnMachineFunction() local
626 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
627 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
647 runOnBlock(MBB, NumRegs); in runOnMachineFunction()
649 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
650 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
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| D | VirtRegMap.cpp | 77 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow() local
78 Virt2PhysMap.resize(NumRegs); in grow()
79 Virt2StackSlotMap.resize(NumRegs); in grow()
80 Virt2SplitMap.resize(NumRegs); in grow()
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| D | MachineRegisterInfo.cpp | 48 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); in MachineRegisterInfo() local
51 UsedPhysRegMask.resize(NumRegs); in MachineRegisterInfo()
52 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); in MachineRegisterInfo()
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| D | MachineLICM.cpp | 529 unsigned NumRegs = TRI->getNumRegs(); in HoistRegionPostRA() local
530 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. in HoistRegionPostRA()
531 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. in HoistRegionPostRA()
558 BitVector TermRegs(NumRegs); in HoistRegionPostRA()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNNSAReassign.cpp | 91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
114 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
116 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
120 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
124 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
131 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
147 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
149 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
151 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
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| D | AMDGPURegisterInfo.h | 31 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
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| D | AMDGPURegisterInfo.cpp | 75 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel, unsigned NumRegs) { in getSubRegFromChannel() argument
76 const unsigned NumRegIndex = NumRegs - 1; in getSubRegFromChannel()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/ |
| D | RegisterFile.cpp | 26 unsigned NumRegs) in RegisterFile() argument
30 initialize(SM, NumRegs);
33 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize() argument
38 RegisterFiles.emplace_back(NumRegs); in initialize()
441 unsigned NumRegs = NumPhysRegs[I]; in isAvailable() local
442 if (!NumRegs) in isAvailable()
452 if (RMT.NumPhysRegs < NumRegs) { in isAvailable()
464 NumRegs = RMT.NumPhysRegs; in isAvailable()
467 if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs)) in isAvailable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 33 unsigned NumRegs = 0; member
42 return makeArrayRef(Order.get(), NumRegs);
90 return get(RC).NumRegs; in getNumAllocatableRegs()
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| D | ExecutionDomainFix.h | 116 const unsigned NumRegs; variable
131 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {} in ExecutionDomainFix()
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| D | LiveVariables.h | 180 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 183 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; in EmitTargetCodeForMemcpy() local
186 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
190 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
191 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
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| D | ARMExpandPseudoInsts.cpp | 129 uint8_t NumRegs; // D registers loaded or stored member
477 unsigned NumRegs = TableEntry->NumRegs; in ExpandVLD() local
503 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVLD()
505 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVLD()
507 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVLD()
588 unsigned NumRegs = TableEntry->NumRegs; in ExpandVST() local
631 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVST()
633 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVST()
635 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVST()
664 unsigned NumRegs = TableEntry->NumRegs; in ExpandLaneOp() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/HardwareUnits/ |
| D | RegisterFile.h | 185 void initialize(const MCSchedModel &SM, unsigned NumRegs);
189 unsigned NumRegs = 0);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMachineFunctionInfo.cpp | 38 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT); in computeLegalValueVTs() local
40 for (unsigned I = 0; I != NumRegs; ++I) in computeLegalValueVTs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 150 unsigned NumRegs; // Number of entries in the array variable
360 NumRegs = NR; in InitMCRegisterInfo()
440 assert(RegNo < NumRegs &&
485 return NumRegs; in getNumRegs()
547 assert(RegNo < NumRegs && in getEncodingValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 199 unsigned NumRegs = TRI.getNumRegs(); in aliasMM() local
203 for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) { in aliasMM()
214 unsigned TailRegs = NumRegs % 32; in aliasMM()
217 unsigned TW = NumRegs / 32; in aliasMM()
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| D | HexagonBlockRanges.cpp | 474 unsigned NumRegs = TRI.getNumRegs(); in computeDeadMap() local
475 BitVector Visited(NumRegs); in computeDeadMap()
476 for (unsigned R = 1; R < NumRegs; ++R) { in computeDeadMap()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 200 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag); in tryInlineAsm() local
201 if (NumRegs) in tryInlineAsm()
218 || NumRegs != 2) in tryInlineAsm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg() local
278 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree); in CC_X86_32_MCUInReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 174 GlobalContext *Ctx, int32_t NumRegs, SmallBitVector TypeToRegisterSet[], in filterTypeToRegisterSet() argument
179 SmallBitVector(NumRegs)); in filterTypeToRegisterSet()
181 SmallBitVector(NumRegs)); in filterTypeToRegisterSet()
184 for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) { in filterTypeToRegisterSet()
240 if (BuildDefs::dump() && NumRegs && in filterTypeToRegisterSet()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 362 const unsigned NumRegs = NumMergeRegs / NumDefs; in tryCombineMerges() local
365 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineMerges()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 377 unsigned NumRegs; in getCopyFromPartsVector() local
380 NumRegs = TLI.getVectorTypeBreakdownForCallingConv( in getCopyFromPartsVector()
384 NumRegs = in getCopyFromPartsVector()
389 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); in getCopyFromPartsVector()
390 NumParts = NumRegs; // Silence a compiler warning. in getCopyFromPartsVector()
711 unsigned NumRegs; in getCopyToPartsVector() local
713 NumRegs = TLI.getVectorTypeBreakdownForCallingConv( in getCopyToPartsVector()
717 NumRegs = in getCopyToPartsVector()
722 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); in getCopyToPartsVector()
723 NumParts = NumRegs; // Silence a compiler warning. in getCopyToPartsVector()
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