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Searched refs:NumVecs (Results 1 – 6 of 6) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp197 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
205 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
213 unsigned NumVecs, const uint16_t *DOpcodes,
266 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
273 unsigned NumVecs, const uint16_t *DOpcodes,
309 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1868 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1869 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1870 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2003 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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DARMISelLowering.cpp13105 unsigned NumVecs = 0; in CombineBaseUpdate() local
13111 NumVecs = 1; break; in CombineBaseUpdate()
13113 NumVecs = 2; break; in CombineBaseUpdate()
13115 NumVecs = 3; break; in CombineBaseUpdate()
13117 NumVecs = 4; break; in CombineBaseUpdate()
13125 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
13127 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
13129 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
13131 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
13133 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp206 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
213 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
215 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
217 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
218 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
220 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
221 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
222 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
223 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1164 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() argument
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DAArch64ISelLowering.cpp11657 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
11662 NumVecs = 2; break; in performNEONPostLDSTCombine()
11664 NumVecs = 3; break; in performNEONPostLDSTCombine()
11666 NumVecs = 4; break; in performNEONPostLDSTCombine()
11668 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
11670 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
11672 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
11674 NumVecs = 2; break; in performNEONPostLDSTCombine()
11676 NumVecs = 3; break; in performNEONPostLDSTCombine()
11678 NumVecs = 4; break; in performNEONPostLDSTCombine()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DVectorUtils.cpp669 unsigned NumVecs) { in createInterleaveMask() argument
672 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
727 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
728 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
734 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
736 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
743 if (NumVecs % 2 != 0) in concatenateVectors()
744 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
747 NumVecs = ResList.size(); in concatenateVectors()
748 } while (NumVecs > 1); in concatenateVectors()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DVectorUtils.h337 unsigned NumVecs);