| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 193 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
194 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitPrologue()
199 .addReg(OffsetReg); in emitPrologue()
247 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
248 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
255 .addReg(OffsetReg); in emitEpilogue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 51 unsigned OffsetReg,
57 unsigned OffsetReg,
247 unsigned OffsetReg) const;
255 unsigned OffsetReg) const;
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| D | R600InstrInfo.cpp | 1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1041 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1046 OffsetReg); in expandPostRAPseudo()
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1055 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1061 OffsetReg); in expandPostRAPseudo()
1116 unsigned OffsetReg) const { in buildIndirectWrite()
1117 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1123 unsigned OffsetReg, in buildIndirectWrite() argument
1134 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| D | SIFrameLowering.cpp | 120 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( in buildPrologSpill() local
123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) in buildPrologSpill()
128 .addReg(OffsetReg, RegState::Kill) in buildPrologSpill()
167 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( in buildEpilogReload() local
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) in buildEpilogReload()
175 .addReg(OffsetReg, RegState::Kill) in buildEpilogReload()
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| D | AMDGPUCallLowering.cpp | 356 Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); in lowerParameterPtr() local
357 B.buildConstant(OffsetReg, Offset); in lowerParameterPtr()
359 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| D | SIRegisterInfo.cpp | 362 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
366 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
372 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
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| D | AMDGPUInstructionSelector.cpp | 2034 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdSgpr() local
2035 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg) in selectSmrdSgpr()
2039 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); } in selectSmrdSgpr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member
176 return Mem.OffsetReg; in getMemOffsetReg()
616 Op->Mem.OffsetReg = 0; in MorphToMemImm()
624 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
628 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
640 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 114 Register OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress() local
115 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | X86ISelLowering.cpp | 30385 unsigned OffsetReg = 0; in EmitVAARG64WithCustomInserter() local
30439 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARG64WithCustomInserter()
30440 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARG64WithCustomInserter()
30450 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
30461 assert(OffsetReg != 0); in EmitVAARG64WithCustomInserter()
30477 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
30488 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 105 Register OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
106 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 566 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
567 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 241 unsigned OffsetReg; member
302 return Mem.OffsetReg; in getMemOffsetReg()
477 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
486 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
498 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 5291 const Variable *OffsetReg, int16_t OffsetRegShAmt, in dumpAddressOpt() argument
5307 if (OffsetReg) in dumpAddressOpt()
5308 OffsetReg->dump(Func); in dumpAddressOpt()
5367 Variable **OffsetReg, int32_t OffsetRegShamt, in matchCombinedBaseIndex() argument
5373 if (*OffsetReg != nullptr) in matchCombinedBaseIndex()
5399 *OffsetReg = Var2; in matchCombinedBaseIndex()
5406 Variable **OffsetReg, OperandARM32::ShiftKind *Kind, in matchShiftedOffsetReg() argument
5415 if (*OffsetReg == nullptr) in matchShiftedOffsetReg()
5417 auto *IndexInst = VMetadata->getSingleDefinition(*OffsetReg); in matchShiftedOffsetReg()
5420 assert(!VMetadata->isMultiDef(*OffsetReg)); in matchShiftedOffsetReg()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 297 Register OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
299 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | MipsSEInstrInfo.cpp | 881 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
895 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| D | MipsISelLowering.cpp | 2549 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2551 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2554 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 159 Register OffsetReg = MRI.createGenericVirtualRegister(s64); in getStackAddress() local
160 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | AArch64InstructionSelector.cpp | 4316 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
4326 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
4357 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
4366 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
4367 OffsetReg = narrowExtendRegIfNeeded(OffsetReg, MIB); in selectExtendedSHL()
4373 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
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| D | AArch64FastISel.cpp | 94 unsigned OffsetReg = 0; member in __anoned81748d0111::AArch64FastISel::Address
120 OffsetReg = Reg; in setOffsetReg()
124 return OffsetReg; in getOffsetReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 166 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
171 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
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| D | HexagonISelLowering.cpp | 2867 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
2873 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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