/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/ |
D | DWARFExpression.cpp | 27 typedef DWARFExpression::Operation Op; in getDescriptions() typedef 28 typedef Op::Description Desc; in getDescriptions() 31 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr); in getDescriptions() 32 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2); in getDescriptions() 33 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1); in getDescriptions() 34 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1); in getDescriptions() 35 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2); in getDescriptions() 36 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2); in getDescriptions() 37 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4); in getDescriptions() 38 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4); in getDescriptions() [all …]
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/third_party/skia/third_party/externals/spirv-headers/include/spirv/unified1/ |
D | spirv.hpp11 | 1169 enum class Op : unsigned { 1821 inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { 1825 case Op::OpNop: *hasResult = false; *hasResultType = false; break; 1826 case Op::OpUndef: *hasResult = true; *hasResultType = true; break; 1827 case Op::OpSourceContinued: *hasResult = false; *hasResultType = false; break; 1828 case Op::OpSource: *hasResult = false; *hasResultType = false; break; 1829 case Op::OpSourceExtension: *hasResult = false; *hasResultType = false; break; 1830 case Op::OpName: *hasResult = false; *hasResultType = false; break; 1831 case Op::OpMemberName: *hasResult = false; *hasResultType = false; break; 1832 case Op::OpString: *hasResult = true; *hasResultType = false; break; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Headers/include/spirv/unified1/ |
D | spirv.hpp11 | 1170 enum class Op : unsigned { 1822 inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { 1826 case Op::OpNop: *hasResult = false; *hasResultType = false; break; 1827 case Op::OpUndef: *hasResult = true; *hasResultType = true; break; 1828 case Op::OpSourceContinued: *hasResult = false; *hasResultType = false; break; 1829 case Op::OpSource: *hasResult = false; *hasResultType = false; break; 1830 case Op::OpSourceExtension: *hasResult = false; *hasResultType = false; break; 1831 case Op::OpName: *hasResult = false; *hasResultType = false; break; 1832 case Op::OpMemberName: *hasResult = false; *hasResultType = false; break; 1833 case Op::OpString: *hasResult = true; *hasResultType = false; break; [all …]
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/third_party/spirv-headers/include/spirv/unified1/ |
D | spirv.hpp11 | 1227 enum class Op : unsigned { 1905 inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { 1909 case Op::OpNop: *hasResult = false; *hasResultType = false; break; 1910 case Op::OpUndef: *hasResult = true; *hasResultType = true; break; 1911 case Op::OpSourceContinued: *hasResult = false; *hasResultType = false; break; 1912 case Op::OpSource: *hasResult = false; *hasResultType = false; break; 1913 case Op::OpSourceExtension: *hasResult = false; *hasResultType = false; break; 1914 case Op::OpName: *hasResult = false; *hasResultType = false; break; 1915 case Op::OpMemberName: *hasResult = false; *hasResultType = false; break; 1916 case Op::OpString: *hasResult = true; *hasResultType = false; break; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenGlobalISel.inc | 894 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 63*/ 7398, 906 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 907 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, 913 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 914 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 915 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, 916 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, 917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, 934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 257 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op); 762 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm() 763 Op.setImm(Val); in CreateImm() 764 return Op; in CreateImm() 768 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm() 769 Op.Contents.CI = CI; in CreateCImm() 770 return Op; in CreateCImm() 774 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm() 775 Op.Contents.CFP = CFP; in CreateFPImm() 776 return Op; in CreateFPImm() [all …]
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D | MachineRegisterInfo.h | 974 MachineOperand *Op = nullptr; variable 976 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator() 988 assert(Op && "Cannot increment end iterator!"); in advance() 989 Op = getNextOperandForReg(Op); in advance() 993 if (Op) { in advance() 994 if (Op->isUse()) in advance() 995 Op = nullptr; in advance() 997 assert(!Op->isDebug() && "Can't have debug defs"); in advance() 1001 while (Op && ((!ReturnDefs && Op->isDef()) || in advance() 1002 (SkipDebug && Op->isDebug()))) in advance() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenGlobalISel.inc | 728 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 64*/ 1359, 739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 746 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 747 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 748 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
D | X86GenGlobalISel.inc | 840 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 60*/ 1754, 859 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 860 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 865 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 877 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 918 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 409 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { in lowerSELECT() argument 411 return MipsTargetLowering::LowerOperation(Op, DAG); in lowerSELECT() 413 EVT ResTy = Op->getValueType(0); in lowerSELECT() 414 SDLoc DL(Op); in lowerSELECT() 419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT() 420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT() 421 Op->getOperand(2)); in lowerSELECT() 449 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument 451 switch(Op.getOpcode()) { in LowerOperation() 452 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenGlobalISel.inc | 1218 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 83*/ 7281, 1230 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1231 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, 1234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, 1235 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, 1247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, 1248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, 1249 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, 1261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, [all …]
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/third_party/json/include/nlohmann/detail/meta/ |
D | detected.hpp | 32 template<class...> class Op, 40 template<class Default, template<class...> class Op, class... Args> 41 struct detector<Default, void_t<Op<Args...>>, Op, Args...> 44 using type = Op<Args...>; 47 template<template<class...> class Op, class... Args> 48 using is_detected = typename detector<nonesuch, void, Op, Args...>::value_t; 50 template<template<class...> class Op, class... Args> 51 struct is_detected_lazy : is_detected<Op, Args...> { }; 53 template<template<class...> class Op, class... Args> 54 using detected_t = typename detector<nonesuch, void, Op, Args...>::type; [all …]
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/third_party/skia/src/opts/ |
D | SkVM_opts.h | 119 STRIDE_1(Op::store8 ): memcpy(args[immA], &r[x].i32, 1); break; in interpret_skvm() 120 STRIDE_1(Op::store16): memcpy(args[immA], &r[x].i32, 2); break; in interpret_skvm() 121 STRIDE_1(Op::store32): memcpy(args[immA], &r[x].i32, 4); break; in interpret_skvm() 122 STRIDE_1(Op::store64): memcpy((char*)args[immA]+0, &r[x].i32, 4); in interpret_skvm() 125 STRIDE_K(Op::store8 ): skvx::cast<uint8_t> (r[x].i32).store(args[immA]); break; in interpret_skvm() 126 STRIDE_K(Op::store16): skvx::cast<uint16_t>(r[x].i32).store(args[immA]); break; in interpret_skvm() 127 STRIDE_K(Op::store32): (r[x].i32).store(args[immA]); break; in interpret_skvm() 128 STRIDE_K(Op::store64): (skvx::cast<uint64_t>(r[x].u32) << 0 | in interpret_skvm() 132 STRIDE_1(Op::load8 ): r[d].i32 = 0; memcpy(&r[d].i32, args[immA], 1); break; in interpret_skvm() 133 STRIDE_1(Op::load16): r[d].i32 = 0; memcpy(&r[d].i32, args[immA], 2); break; in interpret_skvm() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.h | 151 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 159 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 160 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 161 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 162 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 163 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 164 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 165 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 166 SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const; 167 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
D | MCInst.h | 116 MCOperand Op; in createReg() local 117 Op.Kind = kRegister; in createReg() 118 Op.RegVal = Reg; in createReg() 119 return Op; in createReg() 123 MCOperand Op; in createImm() local 124 Op.Kind = kImmediate; in createImm() 125 Op.ImmVal = Val; in createImm() 126 return Op; in createImm() 130 MCOperand Op; in createFPImm() local 131 Op.Kind = kFPImmediate; in createFPImm() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
D | BPFInstPrinter.cpp | 54 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local 55 if (Op.isReg()) { in printOperand() 56 O << getRegisterName(Op.getReg()); in printOperand() 57 } else if (Op.isImm()) { in printOperand() 58 O << formatImm((int32_t)Op.getImm()); in printOperand() 60 assert(Op.isExpr() && "Expected an expression"); in printOperand() 61 printExpr(Op.getExpr(), O); in printOperand() 88 const MCOperand &Op = MI->getOperand(OpNo); in printImm64Operand() local 89 if (Op.isImm()) in printImm64Operand() 90 O << formatImm(Op.getImm()); in printImm64Operand() [all …]
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/third_party/typescript/tests/baselines/reference/ |
D | nonInferrableTypePropagation1.types | 2 type Op<I, O> = (thing: Thing<I>) => Thing<O>; 3 >Op : Op<I, O> 13 >pipe : <A, B>(opA: Op<T, A>, opB: Op<A, B>) => Thing<B> 15 opA: Op<T, A>, 16 >opA : Op<T, A> 18 opB: Op<A, B>, 19 >opB : Op<A, B> 30 declare function map<T, R>(project: (value: T) => R): Op<T, R>; 31 >map : <T, R>(project: (value: T) => R) => Op<T, R> 35 declare function tap<T>(next: (value: T) => void): Op<T, T>; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.h | 108 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 169 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 170 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 171 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 172 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 173 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 174 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 175 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 176 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 177 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyISelLowering.cpp | 93 for (auto Op : in WebAssemblyTargetLowering() 95 setOperationAction(Op, T, Expand); in WebAssemblyTargetLowering() 98 for (auto Op : in WebAssemblyTargetLowering() 100 setOperationAction(Op, T, Legal); in WebAssemblyTargetLowering() 112 for (auto Op : in WebAssemblyTargetLowering() 117 setOperationAction(Op, T, Expand); in WebAssemblyTargetLowering() 120 setOperationAction(Op, T, Expand); in WebAssemblyTargetLowering() 122 setOperationAction(Op, MVT::v2i64, Expand); in WebAssemblyTargetLowering() 128 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering() 130 setOperationAction(Op, T, Legal); in WebAssemblyTargetLowering() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeTypes.cpp | 293 const auto Op = N->getOperand(i); in run() local 294 LLVM_DEBUG(dbgs() << "Analyzing operand: "; Op.dump(&DAG)); in run() 295 EVT OpVT = Op.getValueType(); in run() 497 SDValue Op = OrigOp; in AnalyzeNewNode() local 499 AnalyzeNewValue(Op); // Op may morph. in AnalyzeNewNode() 501 if (Op.getNode()->getNodeId() == Processed) in AnalyzeNewNode() 506 NewOps.push_back(Op); in AnalyzeNewNode() 507 } else if (Op != OrigOp) { in AnalyzeNewNode() 510 NewOps.push_back(Op); in AnalyzeNewNode() 686 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) { in SetPromotedInteger() argument [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelLowering.h | 36 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const; 39 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG); 40 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG); 44 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const; 51 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const; 52 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const; 53 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const; [all …]
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D | R600ISelLowering.h | 35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 72 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 73 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 74 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 75 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 77 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 81 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 82 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 84 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.h | 315 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 328 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, 345 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 375 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 652 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 654 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 699 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 700 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 701 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 702 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.h | 449 void LowerAsmOperandForConstraint(SDValue Op, 498 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 526 void computeKnownBitsForTargetNode(const SDValue Op, 533 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 558 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 559 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG, 561 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 562 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 575 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 576 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
D | SparcAsmParser.cpp | 75 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 379 auto Op = std::make_unique<SparcOperand>(k_Token); in CreateToken() local 380 Op->Tok.Data = Str.data(); in CreateToken() 381 Op->Tok.Length = Str.size(); in CreateToken() 382 Op->StartLoc = S; in CreateToken() 383 Op->EndLoc = S; in CreateToken() 384 return Op; in CreateToken() 389 auto Op = std::make_unique<SparcOperand>(k_Register); in CreateReg() local 390 Op->Reg.RegNum = RegNum; in CreateReg() 391 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; in CreateReg() [all …]
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