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Searched refs:Op2 (Results 1 – 25 of 111) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
346 unsigned Op1, Op2; in Decode2RInstruction() local
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
DNaClBitCodes.h238 const NaClBitCodeAbbrevOp &Op2) {
239 return Op1.Compare(Op2) < 0;
243 const NaClBitCodeAbbrevOp &Op2) {
244 return Op1.Compare(Op2) <= 0;
248 const NaClBitCodeAbbrevOp &Op2) {
249 return Op1.Compare(Op2) == 0;
253 const NaClBitCodeAbbrevOp &Op2) {
254 return Op1.Compare(Op2) != 0;
258 const NaClBitCodeAbbrevOp &Op2) {
259 return Op1.Compare(Op2) >= 0;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
294 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
301 if (Op2.isImm()) { in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDFAPacketizer.cpp283 const MachineMemOperand &Op2, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
295 MemoryLocation(Op2.getValue(), Overlapb, in alias()
296 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
141 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
153 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
156 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
DSelectionDAG.h895 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
901 Ops.push_back(Op2);
1216 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
1217 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1219 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1221 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1245 SDValue Op1, SDValue Op2);
1247 SDValue Op1, SDValue Op2, SDValue Op3);
1258 EVT VT2, SDValue Op1, SDValue Op2);
1282 SDValue Op1, SDValue Op2);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
32 SDValue Chain, SDValue Op1, SDValue Op2,
37 SDValue Chain, SDValue Op1, SDValue Op2,
DWebAssemblyPeephole.cpp162 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
163 if (!Op2.isReg()) in runOnMachineFunction()
168 Register NewReg = Op2.getReg(); in runOnMachineFunction()
DWebAssemblySelectionDAGInfo.cpp37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align, in EmitTargetCodeForMemmove()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/AsmParser/
DBPFAsmParser.cpp268 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
272 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
273 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
274 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
275 || Op2.getToken() == "le64") in PreMatchCheck()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp346 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
348 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
731 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
748 if (!Op2.isReg()) { in splitCombine()
750 .add(Op2); in splitCombine()
753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
783 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
784 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
785 int64_t Sh64 = Op2.getImm(); in splitShift()
907 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMaskingPreRA.cpp232 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair() local
233 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
234 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
235 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
248 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
250 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
251 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
DSIInsertSkips.cpp372 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
379 if (Op2.isImm() && Op2.getImm() != -1) in optimizeVccBranch()
383 if (Op2.isReg()) { in optimizeVccBranch()
384 SReg = Op2.getReg(); in optimizeVccBranch()
401 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DBypassSlowDivision.cpp89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
329 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
333 if (Op1 && Op2) in insertOperandRuntimeCheck()
334 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
336 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCBranchCoalescing.cpp337 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
340 << "Op2: " << Op2 << "\n"); in identicalOperands()
342 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
359 if (Op1.isReg() && Op2.isReg() && in identicalOperands()
361 Register::isVirtualRegister(Op2.getReg())) { in identicalOperands()
363 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp166 MCOperand Op2 = MI.getOperand(2); in getMemoryOpValue() local
167 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
168 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DProfileSummary.cpp130 ConstantAsMetadata *Op2 = in getSummaryFromMD() local
133 if (!Op0 || !Op1 || !Op2) in getSummaryFromMD()
137 cast<ConstantInt>(Op2->getValue())->getZExtValue()); in getSummaryFromMD()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp77 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
118 if (Op2.isImm() && Op3.isImm()) { in printInst()
121 int64_t immr = Op2.getImm(); in printInst()
152 if (Op2.getImm() > Op3.getImm()) { in printInst()
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
170 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
174 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && in printInst()
193 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; in printInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp113 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
523 const MachineMemOperand &Op2) const { in alias()
524 if (!Op1.getValue() || !Op2.getValue()) in alias()
527 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
529 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
533 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); in alias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td553 // Op0 Op1 CRn CRm Op2
618 // Op0 Op1 CRn CRm Op2
657 // Op0 Op1 CRn CRm Op2
668 // Op0 Op1 CRn CRm Op2
674 // Op0 Op1 CRn CRm Op2
679 // Op0 Op1 CRn CRm Op2
686 // Op0 Op1 CRn CRm Op2
705 // Op0 Op1 CRn CRm Op2
711 // Op0 Op1 CRn CRm Op2
716 // Op0 Op1 CRn CRm Op2
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMTInstrFormats.td39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
47 let Inst{10-6} = Op2.Value;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/
DMCTargetAsmParser.h454 const MCParsedAsmOperand &Op2) const { in regsEqual() argument
455 assert(Op1.isReg() && Op2.isReg() && "Operands not all regs"); in regsEqual()
456 return Op1.getReg() == Op2.getReg(); in regsEqual()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DPatternMatch.h1209 T1 Op2; member
1211 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1216 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)); in match()
1226 T1 Op2; member
1229 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1230 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1235 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)) && in match()
1786 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
1787 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1793 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
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